JESD79F
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DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks)
32 M X4 (8 M X4 X4 banks), 16 M X8 (4 M X8 X4 banks), 8 M X16 (2 M X16 X4 banks)
64MX4(16MX4X4banks),32MX8(8MX8X4banks),16MX16(4MX16X4banks)
128MX4(32MX4X4banks),64MX8(16MX8X4banks),32MX16(8MX16X4banks)
256 M X4 (64 M X4 X4 banks), 128 M X8 (32 M X8 X4 banks), 64 M X16 (16 M X16 X4 banks)
FEATURES
• Double--data--rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/re-
ceived with data, to be used in capturing data at
the receiver
• DQS is edge--aligned with data for READs; cen-
ter--aligned with data for WRITEs
• Differential clock inputs (CK and CK
)
• DLL aligns DQ and DQS transitions with CK transi-
tions
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Four internal banks for concurrent operation
• Data mask (DM) f or write data
• Burst lengths: 2, 4, or 8
• CAS Latency: 2 or 2.5, DDR400 also includes
CL = 3
• AUTO PRECHARGE option for each burst access
• Auto Refresh and Self Refresh Modes
• 2.5 V (SSTL_2 compatible) I/O
• VDDQ: +2.5 V ±0.2 V for DDR 200, 266, or 333
+2.6 ±0.1 V for DDR 400
• VDD:
+3.3 V ±0.3 V or +2.5 V ±0.2 V for DDR 200, 266,
or 333
+2.6 ±0.1 V for DDR 400
GENERAL DESCRIPTION
The DDR SDRAM is a high--speed CMOS, dynamic
random--access memory internally configured as a
quad--bank DRAM. These devices contain the follow-
ing number of bits:
64 Mb has 67,108,864 bits
128 Mb has 134,217,728 bits
256 Mb has 268,435,456 bits
512 Mb has 536,870,912 bits
1 Gb has 1,073,741,824 bits
The DDR SDRAMuses a double -- data--rate architec-
ture to achieve high -- s peed operation. The double
data rate architecture is essentially a 2n prefetch archi-
tecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM effectively consists
of a single 2n--bit wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n --bit
wide, one -- half--clock -- cycle data transfers at the I/O
pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge--aligned with data for
READs and center--aligned with data for WRITEs.
The DDR SDRAM operates from a differential clock
(CK and CK
; the crossing of CK going HIGH and CK
going LOW will be referred to as the positive edge of
CK). Commands (address and control signals) are reg-
istered at every positive edge of CK. Input data is regis-
tered on both edges of DQS, and output data is refer-
enced to both edges of DQS, as well as to both edges
of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and
thestartingcolumnlocationfortheburstaccess.
The DDR SDRAM provides for programmable read
or write burst lengths of 2, 4 or 8 locations. An AUTO
PRECHARGE function may be enabled to provide a
self--timed row precharge that is initiated at the end of
the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth
by hiding row precharge and activation time.
An auto refresh mode is provided, along with a pow-
er-- saving, power--down mode. All inputs are compat-
ible with the JEDEC Standard for SSTL_2. All outputs
are SSTL_2, Class II compatible.
Initial devices may have a VDD supply of 3.3 V (nomi-
nal). Eventually, all devices will migrate to a VDD s up-
ply of 2.5 V (nominal). During this initial period of prod-
uct availability, this split will be vendor and device
specific.
This data sheet includes all features and functional-
ity required for JEDEC DDR devices; options not re-
quired, but listed, are noted as such. Certain vendors
may elect to offer a superset of this specification by of-
fering improved timing and/or including optional fea-
tures. Users benefit from knowing that any system de-
sign based on the required aspects of this
specification are supported by all DDR SDRAM ven-
dors; conversely, users seeking to use any superset
specifications bear the responsibility to verify support
with individual vendors.
Note: The functionality described in, a nd the tim-
ing specifications included in this data sheet are
for the DLL Enabled mode of operation.
Note: This specification defines the minimum set of requirements for JEDEC X4/X8/X16 DDR SDRAMs.
Vendors will provide individual data sheets in their specific format. Vendor data sheets should be con -
sulted for optional features or superset specifications.
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