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首页Xtensa Microprocessor Programmer's Guide 中文版.doc
Xtensa Microprocessor Programmer's Guide 中文版.doc
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更新于2023-05-26
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Xtensa Linker Support Packages (LSPs) Xtensa Microprocessor Programmer’s Guide
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Table of Contents
1. 寄存器与指令集...............................................................................................................................................................................................................3
1.1 寄存器分类.................................................................................................................................................................................................................3
1.2 寄存器细分.................................................................................................................................................................................................................3
1.2.1 32-bit 通用寄存器组和窗口寄存器组...............................................................................................................................................................3
1.2.2 32-bit 程序计数器 PC.........................................................................................................................................................................................3
1.2.3 特殊寄存器组.....................................................................................................................................................................................................3
1.2.4 32-bit MAC16 数据寄存器................................................................................................................................................................................4
1.3 指令集.........................................................................................................................................................................................................................4
2. 存储管理和保护...............................................................................................................................................................................................................6
2.1 版本.............................................................................................................................................................................................................................6
2.2 MMU 的功能..............................................................................................................................................................................................................6
2.3 地址转换硬件.............................................................................................................................................................................................................6
2.3.1 全部的 TLB.........................................................................................................................................................................................................6
2.4 存储器访问过程(详见 ISA 4.6.2 节)....................................................................................................................................................................7
2.4.1 选择某个 TLB.....................................................................................................................................................................................................8
2.4.2 查找 TLB.............................................................................................................................................................................................................8
2.4.3 检查访问权限.....................................................................................................................................................................................................8
2.4.4 访问片上存储.....................................................................................................................................................................................................8
2.4.5 访问 PIF..............................................................................................................................................................................................................9
2.4.6 访问 cache.........................................................................................................................................................................................................10
2.5 虚拟地址转换为物理地址的过程...........................................................................................................................................................................10
2.6 Memory-Management Model Types.........................................................................................................................................................................11
2.6.1 TLB 中的 AM 字段...........................................................................................................................................................................................11
2.6.2 术语表...............................................................................................................................................................................................................12
3. 中断和异常.....................................................................................................................................................................................................................13
3.1 异常的硬件结构.......................................................................................................................................................................................................13
3.1.1 PS 寄存器..........................................................................................................................................................................................................13
3.1.2 异常的含义.......................................................................................................................................................................................................14
3.1.3 Windowed Code and Xtensa Processor State....................................................................................................................................................14
3.2 中断分类...................................................................................................................................................................................................................14
3.3 异常之窗口异常.......................................................................................................................................................................................................15
3.3.1 窗口上溢异常和窗口下溢异常的原因...........................................................................................................................................................15
3.3.2 栈帧布局...........................................................................................................................................................................................................16
3.3.3 窗口异常处理函数...........................................................................................................................................................................................16
3.4 使能中断...................................................................................................................................................................................................................16
3.5 处理第 1 个中断.......................................................................................................................................................................................................17
3.5.1 栈的设计及用法...............................................................................................................................................................................................17
3.5.2 UserExceptionVector.........................................................................................................................................................................................17
3.5.3 保存当前状态...................................................................................................................................................................................................17
3.5.4 保存用户栈指针...............................................................................................................................................................................................17
3.5.5 移动 Base Save Area.........................................................................................................................................................................................18
3.5.6 更新栈指针.......................................................................................................................................................................................................18
3.5.7 调用 C 中断处理函数.......................................................................................................................................................................................19
3.5.8 从中断返回.......................................................................................................................................................................................................19
3.6 C 中断处理函数.......................................................................................................................................................................................................19
3.7 嵌套中断的处理.......................................................................................................................................................................................................19
3.7.1 设计思路...........................................................................................................................................................................................................19
3.7.2 对中断处理机制的改动...................................................................................................................................................................................19
3.7.3 栈的设计及用法...............................................................................................................................................................................................19
3.7.4 管理中断软件优先级.......................................................................................................................................................................................20
3.7.5 中断分发机制和 kernel 异常...........................................................................................................................................................................21
3.8 对嵌套中断的理解...................................................................................................................................................................................................21
4. 进程切换.........................................................................................................................................................................................................................22
4.1 进程切换机制...........................................................................................................................................................................................................22
4.2 进程切换机制详解...................................................................................................................................................................................................22
4.3 进程切换代码...........................................................................................................................................................................................................23
《Xtensa System Software Reference Manual Basic Runtime(XTOS) and HAL Reference Manual》读后总结............................................................24
《Xtensa Linker Support Packages(LSPs) Reference Manual》读后总结.......................................................................................................................24
1. 开发流程介绍.................................................................................................................................................................................................................24
2. 开发流程举例.................................................................................................................................................................................................................24
3. LSP 结构..........................................................................................................................................................................................................................26
3.1 LSP 的功能...............................................................................................................................................................................................................26
3.2 LSP 的组成...............................................................................................................................................................................................................26
3.3 存储映射文件的语法...............................................................................................................................................................................................26
3.4 xt-genldscripts 和 xt-regenlsps 的命令格式.............................................................................................................................................................26
4. LSP 对编程阶段的影响..................................................................................................................................................................................................26


1. 寄存器与指令集
1.1 寄存器分类
分为如下 4 类:
(1)32-bit 通用寄存器组和 32-bit 窗口寄存器组;
(2)1 个 32-bit 程序计数器 PC;
(3)特殊寄存器组;
(4)4 个 32-bit MAC16 数据寄存器(212GP,233L,570T);
1.2 寄存器细分
1.2.1 32-bit 通用寄存器组和窗口寄存器组
类型 名称
32-bit 通用寄存器组 AR0, AR1, AR2, AR3, AR4, AR5, AR6, AR7,
AR8, AR9, AR10, AR11, AR12, AR13, AR14, AR15,
AR16, AR17, AR18, AR19, AR20, AR21, AR22, AR23,
AR24, AR25, AR26, AR27, AR28, AR29, AR30, AR31
窗口寄存器组
A0, A1, A2, A3, A4, A5, A6, A7,
A8, A9, A10, A11, A12, A13, A14, A15
1.2.2 32-bit 程序计数器 PC
存放下一条待执行指令的地址。
1.2.3 特殊寄存器组
特殊寄存器存放大部分的处理器状态值。列表如下:
名称
①
描述 需要的配置选项 编号
LBEG Loop-begin address Loop Option 0
LEND Loop-end address Loop Option 1
LCOUNT Loop count Loop Option 2
SAR Shift-amount register Core Architecture 3
BR Boolean registers / register file Boolean Option 4
LITBASE Literal base Extended L32R Option 5
SCOMPARE1 Expected data value for S32C1I Conditional Store Option 12
ATOMCTL Atomic Operation Control Conditional Store Option 99
ACCLO Accumulator low bits MAC16 Option 16
ACCHI Accumulator high bits MAC16 Option 17
M0..3 / MR MAC16 data registers / register file MAC16 Option 32-36
PREFCTL Prefetch Control Prefetch Option 40
WindowBase Base of current AR window Windowed Register Option 72
WindowStart Call-window start bits Windowed Register Option 73
PTEVADDR Page table virtual address MMU Option 83
RASID Ring ASID values MMU Option 90
ITLBCFG Instruction TLB configuration MMU Option 91
DTLBCFG Data TLB configuration MMU Option 92
MMID Memory map ID Trace Port Option 89
IBREAKENABLE Instruction break enable bits Debug Option 96
DDR Debug data register Debug Option 104
IBREAKA0..1 Instruction break address Debug Option 128-129
DBREAKA0..1 Data break address Debug Option 144-145
DBREAKC0..1 Data break control Debug Option 160-161
DEBUGCAUSE Cause of last debug exception Debug Option 233
ICOUNT Instruction count Debug Option 236
ICOUNTLEVEL Instruction count level Debug Option 237
CACHEATTR Cache attribute XEA1 Only – see page 625 98

MEPC Memory error PC register Memory ECC/Parity Option 106
MEPS Memory error PS register Memory ECC/Parity Option 107
MESAVE Memory error save register Memory ECC/Parity Option 108
MESR Memory error status register Memory ECC/Parity Option 109
MECR Memory error check register Memory ECC/Parity Option 110
MEVADDR Memory error virtual addr register Memory ECC/Parity Option 111
EPC1 Level-1 exception PC Exception Option 177
DEPC Double exception PC Exception Option 192
EXCSAVE1 Level-1 exception save location Exception Option 209
EXCCAUSE Cause of last exception Exception Option 232
EXCVADDR Exception virtual address Exception Option 238
EPC2..7 High level exception PC High-Priority Interrupt Option 178-183
EPS2..7 High level exception PS High-Priority Interrupt Option 194-199
EXCSAVE2..7 High level exception save location High-Priority Interrupt Option 210-215
CPENABLE Coprocessor enable bits Coprocessor Context Option 224
INTERRUPT Interrupt request bits Interrupt Option 226
INTSET Set requests in INTERRUPT Interrupt Option 226
INTCLEAR Clear requests in INTERRUPT Interrupt Option 227
INTENABLE Interrupt enable bits Interrupt Option 228
PS Processor state See Table 4-67 on page 100 230
VECBASE Vector Base Relocatable Vector Option 231
CCOUNT Cycle count Timer Interrupt Option 234
CCOMPARE0..2 Cycle number to generate interrupt Timer Interrupt Option 240-242
PRID Processor Id Processor ID Option 235
MISC0..3 Misc register 0-3 Miscellaneous Special Registers Option 244-247
① 用在 RSR, WSR, XSR 指令中
1.2.4 32-bit MAC16 数据寄存器
略
1.3 指令集
下面只包含核心指令集(即每个 Tensilica CPU 都支持)。
指令分类 指令
Load L8UI, L16SI, L16UI, L32I, L32R
Store S8I, S16I, S32I
Memory Ordering MEMW, EXTW
Jump, Call CALL0, CALLX0, RET
J, JX
Conditional Branch BALL, BNALL, BANY, BNONE
BBC, BBCI, BBS, BBSI
BEQ, BEQI, BEQZ
BNE, BNEI, BNEZ
BGE, BGEI, BGEU, BGEUI, BGEZ
BLT, BLTI, BLTU, BLTUI, BLTZ
Move MOVI, MOVEQZ, MOVGEZ, MOVLTZ, MOVNEZ
Arithmetic ADDI, ADDMI,
ADD, ADDX2, ADDX4, ADDX8,
SUB, SUBX2, SUBX4, SUBX8, NEG, ABS
Bitwise Logical AND, OR, XOR
Shift EXTUI, SRLI, SRAI, SLLI
SRC, SLL, SRL, SRA
SSL, SSR, SSAI, SSA8B, SSA8L
Processor Control RSR, WSR, XSR, RUR, WUR, ISYNC, RSYNC, ESYNC, DSYNC
Code Density ADD.N, ADDI.N, BEQZ.N, BNEZ.N, BREAK.N, L32I.N,
MOV.N, MOVI.N, NOP.N, RET.N, RETW.N, S32I.N
Loop LOOP, LOOPGTZ, LOOPNEZ

16-bit Integer Multiply MUL16S, MUL16U
MAC16(qq=HH, HL, LH, or LL) LDDEC, LDINC, MUL.AA.qq, MUL.AD.qq, MUL.DA.qq,
MUL.DD.qq, MULA.AA.qq, MULA.AD.qq, MULA.DA.qq,
MULA.DD.qq, MULS.AA.qq, MULS.AD.qq, MULS.DA.qq,
MULS.DD.qq, MULA.DA.qq.LDDEC, MULA.DA.qq.LDINC,
MULA.DD.qq.LDDEC, MULA.DD.qq.LDINC, UMUL.AA.qq
32-bit Integer Multiply MULL
Integer Divide QUOS, QUOU, REMS, REMU
Miscellaneous CLAMPS (all except 106Micro),
MAX, MAXU, MIN, MINU (all except 106Micro),
NSA, NSAU, SEXT (all except 106Micro)
Multiprocessor Synchronization L32AI, S32RI, S32C1I
Conditional Store S32CI
Exception EXCW, SYSCALL, RFE, FRDE, ILL
Interrupt RSIL, WAITI
High-Priority Interrupt RFI
Instruction Cache IPF, IHI, III, LICT, LICW, SICT, SICW
Instruction Cache Index Lock IPFL, IHU, IIU
Data Cache DPFR, DPFW, DPFRO, DPFWO, DHWB, DHWBI, DIWB, DIWBI, DHI, DII, LDCT, SDCT
Data Cache Index Lock DPFL, DHU, DIU
Region Protection IDTLB, IITLB, PDTLB, PITLB, RDTLB0, RDTLB1, RITLB0, RITLB1, WDTLB, WITLB
MMU IDTLB, IITLB, PDTLB, PITLB, RDTLB0, RDTLB1, RITLB0, RITLB1, WDTLB, WITLB
Debug BREAK, BREAK.N
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