Probing the Design for In-System Debugging.................................................................... 112
Using the Netlist Insertion Debug Probing Flow................................................................ 113
HDL Instantiation Debug Probing Flow Overview.............................................................. 128
Using the HDL Instantiation Debug Probing Flow..............................................................129
Debug Flow in IP Integrator.................................................................................................. 139
Implementing the Design Containing the Debug Cores....................................................142
ILA Core and Timing Considerations.................................................................................... 142
Debug Cores Clocking Guidelines.........................................................................................143
Adding Vivado Debug Cores to a Partial Reconfiguration Design....................................147
Chapter 11: Debugging Logic Designs in Hardware................................148
Using Vivado Logic Analyzer to Debug the Design.............................................................148
Connecting to the Hardware Target and Programming the Device.................................149
Vivado Hardware Manager Dashboards ............................................................................. 150
Setting up the ILA Core to Take a Measurement................................................................ 160
Writing ILA Probes Information............................................................................................ 187
Reading ILA Probes Information...........................................................................................188
Viewing Captured Data from the ILA Core in the Waveform Viewer................................188
Using Waveform ILA Trigger and Export Features............................................................. 188
Saving and Restoring Captured Data from the ILA Core................................................... 191
Enumeration of Probe Values................................................................................................193
Debugging AXI Interfaces in the Hardware Manager........................................................201
Setting Up the VIO Core to Take a Measurement............................................................... 210
Viewing the VIO Core Status..................................................................................................212
Interacting with VIO Core Output Probes............................................................................216
Hardware System Communication Using the JTAG-to-AXI Master Debug Core............. 219
Using Vivado Logic Analyzer in a Lab Environment............................................................222
Description of Hardware Manager Tcl Objects and Commands.......................................223
Using Tcl Commands to Interact with a JTAG-to-AXI Master Core....................................227
Using Tcl Commands to Take an ILA Measurement........................................................... 228
Trigger At Startup....................................................................................................................229
Memory Calibration Debug................................................................................................... 230
Debugging Partial Reconfigurable Designs in Vivado Hardware Manager.....................231
High Bandwidth Memory (HBM) Monitor............................................................................232
Chapter 12: Viewing ILA Probe Data in the Waveform Viewer......... 234
ILA Data and Waveform Relationship...................................................................................234
Waveform Viewer Layout ...................................................................................................... 235
Waveform Viewer Operation ................................................................................................ 236
UG908 (v2019.2) October 30, 2019 www.xilinx.com
Vivado Programming and Debugging 5
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