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Overview

SoC design complexity demands fast and comprehensive verification methods to

accelerate verification and debug, as well as shorten overall schedule and improve

predictability. The VC Formal™ next-generation formal verification solution has the

capacity, speed and flexibility to verify some of the most difficult SoC design challenges,

and includes comprehensive analysis and debug techniques to quickly identify root

causes in the Verdi

debug platform. The VC Formal solution consistently delivers higher

performance and capacity, with more bugs found, more proofs on larger designs and

achieves faster coverage closure through the native integration with VCS

functional

verification solution.

Verification Challenges and Modern Formal Verification

The VC Formal solution includes a comprehensive set of formal applications (Apps),

including Property Verification (FPV), Automatic Extracted Properties (AEP), Coverage

Analyzer (FCA), Connectivity Checking (CC), Sequential Equivalence Checking (SEQ),

Regression Mode Accelerator (RMA), Datapath Validation (DPV), Functional Safety

(FuSa), and a portfolio of Assertion IPs (AIP) for verification of standard bus protocols.

Formal methods are techniques that can perform analysis on the design independent

of, or in conjunction with simulation, and have the power to identify design problems

that can otherwise be missed until very late in the project schedule, or even in the

manufactured silicon, when changes are expensive and debug is highly challenging and

time consuming. When applied early in the design cycle, these methods can identify RTL

issues such as functional correctness and completeness well before the simulation test

environment is up and running.

FPV

FRV

FTA

AEP FCA FXP RMA

FSV

SEQ

Auto Checks

Functional Checks for RTL Structures

Formal Coverage Analyzer

Achieve Faster Coverage Closure

X-Propagation Veriﬁcation

Detects Effects of “X”

Regression Mode Accelerator

Increases veriﬁcation throughput

with faster convergence

Connectivity Checking

Verify IP/SoC Connections

Sequential Equivalence

Verify Clock gating and RTL optimizations

Security Veriﬁcation

Identify Data Leak/Integrity Issues

Property Veriﬁcation

Verify User Deﬁned Properties

Verify Registers against IP-XACT/RALF

Formal Testbench Analyzer

Achieve Formal Signoff with Faults Analysis

DPV

Datapath Validation

Verify Datapath Designs

against the Speciﬁcation

against

the

Speciﬁcation

Integrated HECTOR™ technology

FuSa

Functional Safety Veriﬁcation

Detectable and Diagnosable Faults

Figure 1: VC Formal applications

Delivering the

highest performance

and capacity with

more design bugs

found, more proofs,

and faster coverage

closure

VC Formal

Next-Generation Formal Verification

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ggfysj

2022-05-06

没有什么用，都是官网上的

zhao2118

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