SP601 Hardware User Guide www.xilinx.com UG518 (v1.7) September 26, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
07/15/09 1.0 Initial Xilinx release.
08/19/09 1.1 • Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.
• Updated Figure 1-17.
• Updated Table 1-4, Table 1-19, and Table 1-22.
• Added introductory paragraph to Appendix C, SP601 Master UCF.
• Miscellaneous typographical edits and new user guide template.
05/17/10 1.2 • Updated Figure 1-1, Figure 1-2, Figure 1-14, Figure 1-18, Table 1-9, Table 1-1,
Table 1-11, and Table 1-16.
•Added Figure 1-7, Figure 1-8, and Table 1-13.
• Updated 9. VITA 57.1 FMC-LPC Connector, page 25, Appendix B, VITA 57.1 FMC
LPC Connector Pinout, and Appendix C, SP601 Master UCF.
06/16/10 1.3 Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.
Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. Added
Table 1-26. Added UG394
, Spartan-6 FPGA Power Management User Guide to Appendix D,
References.
09/24/10 1.4 Added Power System Test Points, including Table 1-25.
02/16/11 1.5 Added note and revised header description to indicate the I/Os support LVCMOS25
signaling on page 34. Revised oscillator manufacturer information from Epson to SiTime
on page page 23 and page 51.
07/18/11 1.6 Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in section
Oscillator (Differential), page 23. Added Table 1-15, page 27.
09/26/12 1.7 Added Regulatory and Compliance Information, page 53.
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