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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX2594
SNAS696C –MARCH 2017–REVISED APRIL 2019
LMX2594 15-GHz Wideband PLLATINUM™ RF Synthesizer
With Phase Synchronization and JESD204B Support
1
1 Features
1
• 10-MHz to 15-GHz output frequency
• –110 dBc/Hz phase noise at 100-kHz offset with
15-GHz carrier
• 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
• Programmable output power
• PLL key specifications
– Figure of merit: –236 dBc/Hz
– Normalized 1/f noise: –129 dBc/Hz
– High phase detector frequency
– 400-MHz integer mode
– 300-MHz fractional mode
– 32-bit fractional-N divider
• Remove integer boundary spurs with
programmable input multiplier
• Synchronization of output phase across multiple
devices
• Support for SYSREF with 9-ps resolution
programmable delay
• Frequency ramp and chirp generation ability for
FMCW applications
• < 20-µs VCO calibration speed
• 3.3-V single power supply operation
2 Applications
• 5G and mm-Wave wireless infrastructure
• Test and measurement equipment
• Radar
• MIMO
• Phased array antennas and beam forming
• High-speed data converter clocking (supports
JESD204B)
3 Description
The LMX2594 is a high-performance, wideband
synthesizer that can generate any frequency from 10
MHz to 15 GHz without using an internal doubler,
thus eliminating the need for sub-harmonic filters. The
high-performance PLL with figure of merit of –236
dBc/Hz and high-phase detector frequency can attain
very low in-band noise and integrated jitter. The high-
speed N-divider has no pre-divider, thus significantly
reducing the amplitude and number of spurs. There is
also a programmable input multiplier to mitigate
integer boundary spurs.
The LMX2594 allows users to synchronize the output
of multiple devices and also enables applications that
need deterministic delay between input and output. A
frequency ramp generator can synthesize up to two
segments of ramp in an automatic ramp generation
option or a manual option for maximum flexibility. The
fast calibration algorithm allows changing frequencies
faster than 20 µs. The LMX2594 adds support for
generating or repeating SYSREF (compliant to
JESD204B standard) designed for low-noise clock
sources in high-speed data converters. A fine delay
adjustment (9-ps resolution) is provided in this
configuration to account for delay differences of board
traces.
The output drivers within LMX2594 deliver output
power as high as 7 dBm at 15-GHz carrier frequency.
The device runs from a single 3.3-V supply and has
integrated LDOs that eliminate the need for on-board
low noise LDOs.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMX2594 VQFN (40) 6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
![](https://csdnimg.cn/release/download_crawler_static/11831360/bg2.jpg)
2
LMX2594
SNAS696C –MARCH 2017–REVISED APRIL 2019
www.ti.com
Product Folder Links: LMX2594
Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 6
6 Specifications......................................................... 8
6.1 Absolute Maximum Ratings ...................................... 8
6.2 ESD Ratings.............................................................. 8
6.3 Recommended Operating Conditions....................... 8
6.4 Thermal Information.................................................. 8
6.5 Electrical Characteristics........................................... 9
6.6 Timing Requirements.............................................. 11
6.7 Typical Characteristics............................................ 14
7 Detailed Description............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 39
7.5 Programming........................................................... 40
7.6 Register Maps......................................................... 41
8 Application and Implementation ........................ 59
8.1 Application Information............................................ 59
8.2 Typical Application .................................................. 61
9 Power Supply Recommendations...................... 64
10 Layout................................................................... 65
10.1 Layout Guidelines ................................................. 65
10.2 Layout Example .................................................... 66
11 Device and Documentation Support ................. 67
11.1 Device Support...................................................... 67
11.2 Documentation Support ........................................ 67
11.3 Receiving Notification of Documentation Updates 67
11.4 Community Resources.......................................... 67
11.5 Trademarks ........................................................... 67
11.6 Electrostatic Discharge Caution............................ 67
11.7 Glossary ................................................................ 67
12 Mechanical, Packaging, and Orderable
Information ........................................................... 68
4 Revision History
Changes from Revision B (March 2018) to Revision C Page
• Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values
are not mandatory and the power supply filtering design is up to the user............................................................................ 7
• Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusion ............................................................................. 9
• Changed the names of timing specs to align with timing diagram: changed t
CE
to t
ES
, t
CS
to t
DCS
, t
CH
to t
CDH
, and t
CES
to t
ECS
.................................................................................................................................................................................... 11
• Changed the names of timing specs to align with timing diagram: changed t
ES
to t
CE
, t
CES
to t
ECS
, added t
DCS
and
t
CDH
, and changed t
CS
to t
CR
.................................................................................................................................................. 12
• Changed the serial data input timing diagram and corrected the typo for 'SCK'.................................................................. 12
• Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing
diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4 ..... 12
• Added note for the serial data input timing diagram to explain the t
CE
requirement for mode 4 (CPOL = 1, CPHA = 1)
of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0) ............................................................... 12
• Changed the serial data readback timing diagram............................................................................................................... 13
• Changed the note about MUXout clocking out and emphasized the effect of t
CR
on the readback data available time ..... 13
• Changed the f
OUT
test conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to:
to 14 GHz / 4 = 3.5 GHz ...................................................................................................................................................... 15
• Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graph............................................................ 15
• Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1 ................................................................................................... 21
• Changed description for LD_TYPE. .................................................................................................................................... 21
• Added description of Indirect Vtune. ................................................................................................................................... 22
• Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and
VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registers .............................. 23
• Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear
interpolation under certain conditions................................................................................................................................... 23
• Changed OUTx_PWR Recommendations for Resistor Pullup table ................................................................................... 25
• Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1. .................................................. 29
• Changed description of MASH_SEED ................................................................................................................................ 29
![](https://csdnimg.cn/release/download_crawler_static/11831360/bg3.jpg)
3
LMX2594
www.ti.com
SNAS696C –MARCH 2017–REVISED APRIL 2019
Product Folder Links: LMX2594
Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated
Revision History (continued)
• Added 10-ms wait time before re-programming register R0 in recommended initial power-up sequence ......................... 40
• Added the General Programming Requirements section based on frequently asked questions......................................... 40
• Changed register R4 in the register map to: exposed ACAL_CMP_DLY ........................................................................... 41
• Changed the register R20[14] value from 0 to 1 in the full register map to match the R20 register description ................ 41
• Changed the default value of R25 to align with register map of LMX2595. This change has no impact on the LMX2594. 42
• Changed the R0[14] register field name in the register map from VCO_PHASE_SYNC_EN to VCO_PHASE_SYNC.
to align with the rest of the data sheet ................................................................................................................................. 46
• Added recommended value for register CAL_CLK_DIV when lock time is not of concern.................................................. 46
• Changed the typo for register 'VCO_DACISET' in the register map. Bit 0 of this register was not included in the
map. The full register map and register description were correct ........................................................................................ 48
• Added description to the R4[15:8]: ACAL_CMP_DLY register............................................................................................. 48
• Deleted the bit description '0: disabled; 1: enabled' for register 'PLL_N' ............................................................................. 49
• Added description to the R60[15:0] LD_DLY register .......................................................................................................... 51
• Changed the R31[14] register name from CHDIV_DIV2 to SEG1_EN to align with the naming in the TICS Pro GUI ....... 53
• Changed the R105[1:0] field name from RAMP_NEXT_TRIG to RAMP1_NEXT_TRIG..................................................... 58
• Added the Bias Levels of Pins table..................................................................................................................................... 64
Changes from Revision A (August 2017) to Revision B Page
• Changed all the VCO Gain typical values in the Electrical Characteristics table. This is due to improved
measurement methods and NOT a change in the device itself ........................................................................................... 11
• Moved the high-level output voltage parameter V
CC
– 0.4 value from the MAX column to the MIN.................................... 11
• Moved the high-level output current parameter 0.4 value from the MIN column to the MAX .............................................. 11
• Changed bulleted text: data is clocked out on MUXout, not SDI pin ................................................................................... 13
• Added comment that OSCin is clocked on rising edges of the signal. and reformatted with bulleted list ........................... 19
• Added description of the state machine clock ..................................................................................................................... 20
• Changed example from: 200 MHz / 2
32
to: 200 MHz / (2
32
– 1) .......................................................................................... 21
• Changed LD_DLY description in Table 4 and removed duplicated text in the Lock Detect section.................................... 21
• Changed name from VCO_AMPCAL to VCO_DACISET_STRT ........................................................................................ 23
• Added more programmable settings to Table 5 ................................................................................................................... 23
• Changed VCO Gain table..................................................................................................................................................... 24
• Added that OUTx_PWR states 32 to 47 are redundant and reworded section ................................................................... 25
• Added term "IncludedDivide" for clarity ............................................................................................................................... 26
• Changed Fixed Diagram to show SEG0, SEG1, SEG2, and SEG3 ................................................................................... 27
• Changed included channel divide to IncludedDivide and 2 X SEG0 to 2 X SEG1. Also clarified IncludedDivide
calculations........................................................................................................................................................................... 29
• Added more description on conditions for phase adust ....................................................................................................... 29
• Changed text from: (VCO_PHASE_SYNC = 1) to: (VCO_PHASE_SYNC = 0) ................................................................. 29
• Changed text so the user does not incorrectly assume that MASH_SEED varies from part ot part ................................... 30
• Changed the RAMP_THRESH programming from: 0 to ± 2
32
to: 0 to ± 2
33
– 1 .................................................................. 30
• Removed comment that RAMP_TRIG_CAL only applies in automatic ramping mode........................................................ 30
• Changed the RAMP_LOW and _HIGH programming from: 0 to ± 2
31
to: 0 to ± 2
33
– 1...................................................... 30
• Changed description to be in terms of state machine cycles............................................................................................... 31
• Changed RAMP_MODE to RAMP_MANUAL in the Manual Pin Ramping and Automatic Ramping sections.................... 31
• Added that the RampCLK pin input is reclocked to the phase detector frequency.............................................................. 31
• Added that RampDir rising edges should be targeted away from rising edges of RampCLK pin........................................ 31
• Changed programming enumerations for RAMP0_INC and RAMP1_INC .......................................................................... 33
![](https://csdnimg.cn/release/download_crawler_static/11831360/bg4.jpg)
4
LMX2594
SNAS696C –MARCH 2017–REVISED APRIL 2019
www.ti.com
Product Folder Links: LMX2594
Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
• Changed programming enumerations for RAMP_THRESH, RAMPx_LEN, and RAMP1_INC............................................ 34
• Changed Figure 29 .............................................................................................................................................................. 34
• Changed SysRef description ................................................................................................................................................ 35
• Added divide by 2 to figure................................................................................................................................................... 35
• Changed some entries in the table ...................................................................................................................................... 35
• Changed f
INTERPOLATOR
SYSREF setup equation in Table 18 .............................................................................................. 35
• Changed SysRef delay from: 224 and 225 to: 225 and 226................................................................................................ 36
• Changed "generator" mode to " master " mode. They mean the same thing ........................................................................ 36
• Changed description for SYSREF_DIV................................................................................................................................ 36
• Changed Figure 31 .............................................................................................................................................................. 37
• Changed wording for repeater mode and master mode....................................................................................................... 38
• Changed description of a few of the steps........................................................................................................................... 39
• Changed typo in R17 and R19 ............................................................................................................................................ 48
• Deleted reference to VCO_SEL_STRT_EN. This is always 1 ............................................................................................. 48
• Added VCO_SEL_STRT_EN reference. This is always 1 ................................................................................................... 48
• Changed the enumerations 0-3 and added content to the INPIN_LVL field description ..................................................... 50
• Added Divide by 1' to SYSREF_DIV_PRE register description. Also fixed the name misspelling ...................................... 52
• Deleted redundant formula for Fout and also clarified SYSREF_DIV starts at 4 and counts by 2 ...................................... 52
• Deleted reference to VCO_CAPCTRL_EN, which is always 1, and clarified....................................................................... 54
• Changed text from: f
MAX
to: f
HIGH
........................................................................................................................................... 55
• Changed text from: RAMP_LIMIT_LOW=2
32
- (f
LOW
- f
VCO
) / f
PD
× 16777216 to: RAMP_LIMIT_LOW=2
33
- 16777216
x (f
VCO
- f
LOW
) / f
PD
................................................................................................................................................................ 55
• Removed the OSCin Configuration table and added content to the OSCin Configuration section...................................... 59
• Changed pin 27 recommendation from 10 µF to 1 µF in Figure 51..................................................................................... 61
Changes from Original (March 2017) to Revision A Page
• Added DAP pin described as "Die Attach Pad"...................................................................................................................... 7
• Added H2 Spec for 11 GHz ................................................................................................................................................... 9
• Clarified that output power assumes that load is matched and losses are de-embedded..................................................... 9
• Changed "SDA" pin name mispelled. Should be "SDI". Also fixed in timing diagrams. Also added CE Pin ...................... 11
• Swapped SDI and SCK in diagram ..................................................................................................................................... 12
• Added graphs and reordered ............................................................................................................................................... 14
• Added 12-GHz VCO frequency for PLL Noise Metrics Plot ................................................................................................ 14
• Added Phase Noise plots vs. Temperature ......................................................................................................................... 15
• Added Phase noise vs. Fpd Graph ..................................................................................................................................... 16
• Moved second paragraph of Readback into Lock Detect section; deleted last paragraph of Readback (was in wrong
place).................................................................................................................................................................................... 22
• Changed table to allow 11.5 GHz max frequency for divides >6 ......................................................................................... 24
• Added Recommendations table .......................................................................................................................................... 25
• Changed the IncludedDivide table........................................................................................................................................ 26
• Added section on fine tune adjustments ............................................................................................................................. 30
• Changed graphic and description......................................................................................................................................... 35
• Added SYSREF_EN = 1 if and only if OUTB_MUX=2 ........................................................................................................ 36
• Changed SysRef Example Description and Pictures .......................................................................................................... 38
• Added recommendation to make f
Interpolator
a multiple of f
OSC
.............................................................................................. 39
• Added SEG1_EN.................................................................................................................................................................. 42
• Added INPIN_IGNORE, INPIN_LVL, and INPIN_HYST ...................................................................................................... 43
![](https://csdnimg.cn/release/download_crawler_static/11831360/bg5.jpg)
5
LMX2594
www.ti.com
SNAS696C –MARCH 2017–REVISED APRIL 2019
Product Folder Links: LMX2594
Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated
• Removed RAMP0_FL from register map ............................................................................................................................. 45
• Changed address for VCO_DACISET_STRT and VCO_CAPCTRL .................................................................................. 48
• Clarified MASH_RESET_N. 0 = RESET (integer mode), 1 = Fractional mode .................................................................. 49
• Changed OUT_ISEL to OUTI_SET ..................................................................................................................................... 50
• Added SYSREF_EN=1 when OUTB_MUX=2 ..................................................................................................................... 50
• Added section for input register descriptions ...................................................................................................................... 50
• Added description for SEG1_EN ......................................................................................................................................... 53
• Fixed TYPO table to match main register map. ................................................................................................................... 53
• Added SEG1_EN.................................................................................................................................................................. 53
• Corrected RAMP_BURST_TRIG description to match other place in data sheet................................................................ 56
• Removed duplicate error in R101[2] .................................................................................................................................... 57
• Changed RAMP1_INC from RAMP0 to RAMP1 .................................................................................................................. 57
• Clarified that the delay was in state machine cycles............................................................................................................ 57
• Swapped 1 and 3 in the R110[10:9] description .................................................................................................................. 58
• Fixed pin names in schematic ............................................................................................................................................. 61
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