GD5F1GQ4UAYIG_Rev1.3.pdf

SPI(x1/x2/x4) NAND Flash GD5F1GQ4UAYIG

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SPI (Serial Peripheral Interface) NAND Flash Memory

FEATURE

◆

1G-bit Serial NAND Flash

◆

Program/Erase/Read Speed

-128M-byte -Page Program time: 400us typical

-2048 bytes page for read and program, spare 64bytes -Block Erase time: 3ms typical

-(128K + 4K)bytes per block for erase -Page read time: 120us maximum(w/I ECC)

-108MHz for fast read with 30PF load -2kbyte cache for fast random read

◆ Software/Hardware Write Protection ◆ Advanced Feature for NAND

-Write protect all/portion of memory via software -Internal ECC option, per 512bytes

-Enable/Disable protection with WP# Pin -Internal data move by page with ECC

◆

Advanced security Features

-8K-Byte OTP Region

SPI(x1/x2/x4) NAND Flash GD5F1GQ4UAYIG

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storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive

alternative to SPI-NOR and standard parallel NAND Flash, with advanced features:

remains the same pinout from one density to another. The command sets resemble common SPI-NOR command sets,

modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate

from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to

I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a

the status of device operation.

8– LEAD WSON

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SPI(x1/x2/x4) NAND Flash GD5F1GQ4UAYIG

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Pin Name I/O Description

CS# I

Chip Select input, active low

SO/SIO1 I/O Serial Data Output / Serial Data Input Output 1

WP#/SIO2 I/O Write Protect, active low / Serial Data Input Output 2

VSS Ground Ground

SI/SIO0 I/O Serial Data Input / Serial Data Input Output 0

memory

NAND

ARRAY ORGANIZATION

Each device has Each block has Each page has

SPI(x1/x2/x4) NAND Flash GD5F1GQ4UAYIG

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Note:

addressed.

SPI(x1/x2/x4) NAND Flash GD5F1GQ4UAYIG

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timing diagrams shown in this data sheet are mode 0. See figure2 for more details.

Figure2. SPI Modes Sequence Diagram

CPOL CPHA

00

11

Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven

LOW.

Standard SPI

SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow

data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command

the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.

Quad SPI

data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command

high and then CS# must be at low.