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F
SPECTRUM DIGITAL INCORPORATED
509532-0001
Tuesday, June 24, 2008 1 43
B
DAVINCI HD Evaluation Module
TITLE SHEET
SHEET01 - TITLE
SHEET02 - JTAG EMULATION CONNECTORS
SHEET03 - DSP CLKS/RST/EMU
SHEET04 - DSP SERIAL I/O
SHEET05 - DSP USBII
SHEET06 - DSP EMIF/PCI
SHEET07 - DSP DDR Interface
SHEET08 - DSP VIDEO Ports
SHEET09 - DSP ENET
SHEET10 - DSP POWER PINS
SHEET11 - DSP DECOUPLING CAPS
SHEET12 - BOOT DIP SWITCHES
SHEET13 - I2C EXP,SPI EEPROM, I2C ROMS
SHEET14 - DDR2 MEMORIES
SHEET15 - NAND-FLASH
SHEET16 - CONTROL LOGIC
SHEET17 - ENET DAUGHTER CARD CONN
SHEET18 - ENETCONTROLLER
SHEET19 - ENET POWER
SHEET20 - ENET OUTPUT CONN
SHEET21 - RS232/IR RECEIVER
SHEET22 - USBII INTERFACE
SHEET23 - ATA INTERFACE
SHEET24 - PCI-MUX
SHEET25 - PCI-MUX II
SHEET26 - PCI-CONNECTOR
SHEET27 - VLYNQ CONNECTOR
SHEET28 - AIC32
SHEET29 - SPDIF
SHEET30 - VIDEO CLOCKS
SHEET31 - VIDEO INPUT MUXING
SHEET32 - TVP7002
SHEET33 - TVP5147 COMPOSITE
SHEET34 - TVP5147 II S-VIDEO
SHEET35 - VIDEO OUTPUT MUXING
SHEET36 - ADV7343
SHEET37 - COMPOSITE/S-VIDEO BUFFERING
SHEET38 - COMPONENT VIDEO BUFFERING
SHEET39 - VIDEO DAUGHTER CARD CONN
SHEET40 - I/O DAUGHTER CARD CONN
SHEET41 - DSP CORE POWER
SHEET42 - POWER 1V8, 3V3
SHEET43 - POWER IN, RESET SUPERVISOR
SCHEMATIC CONTENTS
REV
ENGR
2
REVISION STATUS OF SHEETS
1
11
SH
DATE
14 12 13
DATE
ENGR-MGR
MFG
7
DWN
DATE
8
DATE
10
SH
DATE
CHK
RLSE
APPLICATION
REV
35
NEXT ASSY
DATE
6
DATE
9
QA
USED ON
4
15
FFF FF
FFFF
R.R.P.
T.W.K.
R.R.P.
R.R.P.
C.M.D.
R.R.P.
R.R.P.
01/15/2007
01/15/2007
16 17 18 19 20
21 22 23 24 25 01/15/2007
01/15/2007
01/15/2007
01/15/2007
01/15/2007
REV
SH
FFFFFFF
FF
26 27 28 29 30
FF
31 32
F
F
FF
F
FFF
FFF
F
33 34
FF
35 36 37
FFF
REV
REV
SH
SH
FFF
FF
38 39 40
41 42
F
43
RRP05/25/07
Initial schematic for layout
DESCRIPTIONREV APPROVEDDATE
04/30/07 RRP
Initial schematic updated after initial pwb build
SHEET
28
33
34
13
16
13
TVP5147 II
IO EXPANDER 0
EMBEDDED I2C REGISTER 1
I2C ROM
AIC32
TVP5147 I
0x50
BASE
0x18
0x5D
0x5C
0x38 (LEDS/USER_SW)
0x3A
I2C ADDRESS TABLE
B2. USB layer 90 ohm differential
4. ALL 0.1 uF AND 0.01uF CAPACITORS
ARE DECOUPLING CAPS UNLESS
OTHERWISE NOTED. THEY ARE SHOWN
ON THE PAGE WITH THE INTEGRATED
CIRCUITS THEY SHOULD BE PLACED NEAR.
NOTES, UNLESS OTHERWISE SPECIFIED:
1. RESISTANCE VALUES IN OHMS.
2. CAPACTITANCE VALUES IN MICROFARADS.
3. LAST REFERENCE DESIGNATORS :
5. OBSERVE THE FOLLOWING LAYOUT NOTES:
1. TOP - SIGNAL ROUTING
2. GROUND PLANE
3. INNER1 - SIGNAL ROUTING
4. GROUND PLANE
5. INNER2 - SIGNAL ROUTING
6. INNER3 - SIGNAL ROUTING
7. VCC PLANE 1
8. VCC PLANE 2
9. INNER4 - SIGNAL ROUTING
10. INNER5 - SIGNAL ROUTING
6. BOARD PROPERTIES
B1. General layers 50 +/- 5 OHM
MATCHED IMPEDANCE
C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING
D. INNER LAYERS 1.0 OZ CU
E. FR4 BOARD MATERIAL
F. MINIMUM TRACE WIDTH/SPACING 4 MILS
G. MINIMUM VIA SIZE 10/19 MIL
H. LAYER STACKUP:
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE
A. FOLLOW USB APNOTE GUIDELINES
B. FOLLOW DDR2 APNOTE GUIDELINES
0x2A ADV7343
0x6C CDCE949
36
30
MEMORY MAP
11. GROUND PLANE
12. INNER5 - SIGNAL ROUTING
13. GROUND PLANE
14. BOTTOM - SIGNAL ROUTING
0000 0000
ARM RAM
8000 0000 DDR2 RAM - 256 Megabytes
( 1st half of 512 Megabytes )
C000 0000
4200 0000
NAND FLASH EMCS2
4C00 0000
VLYNQ REMOTE DEVICES
3000 0000
PCI ADDRESS SPACE
RESERVED
I2C ADDRESS MAP
THS7303 - OUTPUT
THS7353 - INPUT
TVP7002
32
32
370x2C
0x5D
0x2E
B
A
0x3B
0x3C
16
16
EMBEDDED I2C REGISTER 2
EMBEDDED I2C REGISTER 3
DDR2 RAM - ( 512 Megabytes optional )
A000 0000
C
07/05/07PRE-PRODUCTION RELEASE RRP
D
ADV7343 CHANGE TO INTERNAL REFERENCE RRP08/15/07
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