论文研究-数字集成电路综合及物理设计阶段的时序收敛方案 .pdf

of digita IC is discussed. Timing closure is one of the most important task in digital integrated circuit

design. As integrated circuit develops into the deep sub-micron period, the size of chip and the

complexity of design has increased significantly. As a consequence of this, it becomes more and more

synthesis and physical design based on low-level image processing SoC design. This paper firstly

introduces the way that Design Compiler and IC Compiler use to perform timing analysis, followed by

a discussion of how to use the tool to set reasonable constraints on the design, and finally introduces

the solutions to timing violations in various stages. This SoC has finally got timing closure by using

年来的数字集成电路设计经验，提出了一种数字集成电路设计中，综合以及布局布线阶段的