I
Preface
n the last several decades, information technologies have experienced revolutionary progress, improved
people’s lives, and changed people’s thinking. Demand for electronic devices with better
performance, functionality, and mobility increased to a higher level. Since the invention of the integrated
circuit (IC) in 1958 and, especially, the invention of the personal computer in the 1970s, the design,
manufacture, and applications of IC products thoroughly changed our society, ushering in the information
era. Most of us cannot imagine how to live without the help of ICs and related products, such as personal
computers, televisions, mobile phones, automobiles, and global positioning systems.
The expectation of more powerful IC products leads to requirements for the semiconductor industry to
make ICs with higher transistor (device) density and better performance, as predicted by Moore’s Law.
Since it was first proposed in 1965, Moore’s Law has successfully predicted and governed the technology
roadmap for integrated circuits. Increases in transistor count and improvements in IC performance are
typically enabled by shrinking the transistor-gate critical dimension (CD) using lithography. Ever-decreasing
lithography-exposure wavelengths, supplemented by techniques such as immersion and double patterning,
have driven the CD roadmap. This is getting increasingly challenging and cost prohibitive. The adoption
schedule of next-generation lithography, such as extreme ultraviolet lithography (EUVL), has been postponed
several times because of the technological challenges. This poses a challenge as we attempt to cram more
functionality (and, hence, more transistors) onto the chip.
IC performance is also limited by resistance-capacitance (RC) delays. Copper interconnects and low-
dielectric-constant dielectric materials are extensively used to address this challenge. In recent years, progress
on RC-delay improvement is slower than that on gate delay, causing RC delay to become the dominant
factor for improving IC performance. Leading-edge consumer electronic-products applications need to
deliver more functionality, deliver at faster speeds, be energy efficient, and also fit within smaller
dimensions. Computer system boards are being increasingly populated with multicore processors to boost
performance. Such processors need to be supported by/partnered with low-latency and dense DRAM
memory. Accelerated data exchange, reduced power consumption, and much higher input/output densities
are all enabled by chips interconnected with each other (at micron scale, unlike wires, which are at
millimeter scale) by 3D integration using through-silicon-via (TSV) technology. This integration technology
broadly enables connections between memory-to-memory, microprocessor unit (MPU) to memory, analog-
to-digital chips and ICs having different substrate materials, as well as devices like CMOS image sensors
and microelectromechanical systems (MEMS). The performance and application space makes 3D IC
stacking technology very attractive and can be termed as extending the semiconductor industry “beyond
Moore’s Law.”
3D IC stacking technology is new to the mainstream high-volume semiconductor industry. It involves
most IC fabrication processes—e.g., etching holes to create TSVs, coating them with dielectric and barrier
liners, depositing a seed layer, and filling them with conducting material. Besides the technological
challenges, cost control is also an important criterion for the adoption of this new technology.
In this book, wafer-to-wafer 3D IC stacking technology using TSVs is explained in detail. The book
consists of 11 chapters, covering the technology overview, IC product design and tools, manufacturing-