5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A
VNN
V1P05A
SLP_S0IX_N
NC_+VDDQ_VTT
DDR VTT VR
EN
TPS51206
+VDLP
VBAT
DLP_EN
DRAMPWROK
VCCAPWROK
SOC
CherryTrail-T4
PLT_RST_N
V1P8A
VDDQ_VR
V3P3A
V1P15
VGG
VCC0
VCC1
SOC_PWRBTN_N
13
14
15
16
17
20
21
22
23
18
19
21
24
26
7BAT
8BAT
9BAT
ISL9237
Battery Pack
Battery
Charger
+VCHG_PWR
VBAT
3AC
1BAT
AC Brick
+VDC
System VR
LDO
EN
EC_RTC
AC_OK
4AC
+V3.3AL
5
PWR_SW
4BAT
EC_PWRBTN_IN_N
EC_5VA_EN
6AC
+V5P0AL
7AC
+VSYS
VSYS_EN
8AC
VSYS_PGOOD
9AC
11
1.8LDO
EN
RT9073A
+V3.3AL
+V1P8_EC
RT7290A
RT7291A
RT6220A
IT8110E
EC/KBC
PMIC
Whiskey Cove CHT
PWRBTN_IN_N
RSMRST_N
EC_PWR_LATCH
MP01 Power Up Sequence Diagram
VSYS_EN
EC[O]
+VSYS
VSYS_PGOOD
EC[I]
T10
SDWN#
PLTRST#
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
SOC[O]
SOC[O]
SOC[O]
+VDDQ_VTT
+V1P8_EC
Power On Sequence (Adapter mode)
RTC_RST#
+VRTC_LDO
Enable:
AD+
+V3P3AL
V5P0A_EN
+V5P0AL
PRESS POWER BUTTON
EC[O]
EC[I]
PM_PWRBTN#
PWRSW#
External Power button active
EC output active signal to PMIC
：
1.126s
V1P8A
VDDQ_VR
T15
SLP_S0IX_B
V3P3A
RSMRST#
SUSPWRDNACK
SOC[O]
T17
RSMRST# to SLP_S0IX_B
：
102.21ms
V1P15
VGG
VCC0
VCC1
VCCAPWROK
COREPWROK
T19
VGG to VCC0
：
2ms
T22
SLP_S0IX_B to V1P15
：
100us
T26
MODEMOFF# to SDWN#:25us
MODEMOFF#
DRAMPWROK
SOC[O]
RSMRST# to DRAMPWROK
：
500us
VNN
V1P05A
Power On Sequence (Battery mode)
RTC_RST#
+V3.3A_RTC
PWRSW#
PRESS POWER BUTTON
Other sequences are same as adapter mode
+V3P3AL
VSYS_EN
V5P0A_EN
VSYS_PGOOD
+V5P0AL
EC_PWR_LATCH
PM_PWRBTN#
Enable: PWR_SW#
EC[O]
EC[I]
EC[O]
EC[O]
EC[O]
Power OFF Sequence (Adapter mode)
SoC Controlled
PMIC Controlled
(Cold Off TLP)
PMIC
STATE
+VRTC_LDO 1
PLTRST#
SLP_S0IX_B
COREPWROK
VCCAPWROK
VCC0
VCC1
VGG
V1P15
SUSPWRDNACK
DRAMPWROK
RSMRST#
V3P3A
VDDQ_VR
V1P8A
V1P05A
VNN
SDWN#
MODEMOFF#
VSYS_EN
+V5P0AL 1
+V1P8_EC 1
+V3P3AL 1
+VSYS
T0
Mechanical Off
T18
T9
T11
+VDDQ_VTT
SOC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
PMIC[O]
Other sequences are same as adapter mode
RSMRST#
VSYS_EN
+VSYS
VSYS_PGOOD
+V5P0AL
EC_PWR_LATCH
+V3P3AL
+VRTC_LDO 1
+V1P8_EC
Power OFF Sequence (Battery mode)
20
S0 to CS Sequence
+VRTC_LDO 1
+VSYS 1
SLP_S0IX_B
PLTRST# 1
S0
S0IX
VCCAPWROK 1
S0
VNN
VCC0
VCC1
VGG
V1P15
VCCAPWROK 0
VCCAPWROK 1
T1
VCCRTC stable to RTCRST# de-assetion: 24ms
T01
T02 V3P3AL to V3P3AL_PGOOD: 2.5ms
V3P3AL_PGOOD
T03
V3P3AL to V1P8_EC: -450us
V5P0A_EN to +V5P0AL: 1.27ms
T04
T05 PWRSW# to VSYS_EN: 1.117s
T06
VSYS_EN to VSYS: 703us
T07
VSYS to VSYS_PGOOD: 664.93us
T08
SOC_PWRBTN_N
T09 PMIC output active signal to SOC
：
500ms
PMIC[O]
SOC_PWRBTN_N output active signal to VNN
：
50ms
T11
VNN to V1P05A
：
522.45us
T12
V1P05A to V1P8A
：
1.156ms
V1P8A to VDDQ_VR
：
4.869ms
T13
T14
VDDQ_VR to V3P3A
：
457.81us
V3P3A to RSMRST#
：
1.622ms
0
T16
T18
SLP_S0IX_B to VDDQ_VTT
：
50.7us
T20
VDDQ_VTT to V1P15
：
997.74us
T21 V1P15 to VGG:1.28ms
T23VCC0 to VCC1:939.54us
T24VCC1 to VCCAPWROK:428.51us
together
T25
COREPWROK to MODEMOFF#:517.4ns
T27 SDWN# to PLTRST#:13.738ms
PLTRST# to SLP_S0IX_B:24.7ns
SLP_S0IX_B to VDDQ_VTT:1ms
VDDQ_VTT to COREPWROK:1ms
T1
T2
T3
COREPWROK to VDDQ_VTT:248.2ns
T4
VDDQ_VTT to VCC0:35.577ms
T5
VCC0 to VCC1:37.131ms
VCC1 to VGG:10ms
T6
T7 VGG to V1P15:11.53ms
T8 V1P15 to SUSPWRDNACK:2.17s
DRAMPWROK to SUSPWRDNACK:2.17s
DRAMPWROK to RSMRST#:25.6usT10
RSMRST# to V3P3A:1.118ms
T12 V3P3A to VDDQ_VR:1.0319ms
T13
VDDQ_VR to V1P8A:3.554ms
T14 V1P8A to V1P05A:342.38us
T15
VNN to V1P05A:7.07ms
T16 V1P05A to VNN:1.25ms
together
T17 SDWN# to VSYS_EN:2.05s
VSYS_EN to VSYS:2ms
VCCRTC stable to RTCRST# de-assetion: 24.88ms
PWRSW# to V3P3AL: 1ms
T02
T03
V3P3AL to EC_PWR_LATCH: 160.75ms
T04
EC_PWR_LATCH to VSYS_EN: 1.17s
VSYS_EN to VSYS_PGOOD: 1.4084ms
T05
T06
V5P0A_EN to VSYS_PGOOD: 1.278ms
T07
V5P0A_EN to V5P0AL: 280ms
T08
EC output active signal to PMIC:135ms
VSYS_EN to VSYS:9.96ms
T2
T3
VSYS to VSYS_PGOOD:6.96ms
T4
VSYS_PGOOD to V5P0AL :3.48ms
T5
V5P0AL to EC_PWR_LATCH :100ms
T1
RSMRST# to VSYS_EN:100ms
together
T6 V3P3AL L to V1P8_EC :50us
AC Brick
3.3buck
EN
BL9342
VCC3A_PD
V3P3AL_PGOOD_#
VCC3A_PD
1AC
2AC
2AC
5V_IN
20V_IN4AC
5AC
6AC
6
10AC
7AC
11
12
11
12
COREPWROK
25
2BAT
3BAT
10BAT
T01
Design Title
SizeDocument Number
Rev
Page Date : Sheet : of
Author :Design Date :
Page Name :
Project Name :
Madigi
V1.0
Cherry Trail
Custom
4 38Thursday, October 13, 2016
NormanThursday, October 13, 2016
04_POWER SEQUENCE
MP01
<Doc>
Design Title
SizeDocument Number
Rev
Page Date : Sheet : of
Author :Design Date :
Page Name :
Project Name :
Madigi
V1.0
Cherry Trail
Custom
4 38Thursday, October 13, 2016
NormanThursday, October 13, 2016
04_POWER SEQUENCE
MP01
<Doc>
Design Title
SizeDocument Number
Rev
Page Date : Sheet : of
Author :Design Date :
Page Name :
Project Name :
Madigi
V1.0
Cherry Trail
Custom
4 38Thursday, October 13, 2016
NormanThursday, October 13, 2016
04_POWER SEQUENCE
MP01
<Doc>
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