目 录
前 言 .............................................................................................................................................................. 2
1 总则 .......................................................................................................................................................... 3
2 职责 .......................................................................................................................................................... 3
3 目的 .......................................................................................................................................................... 3
4 内容 .......................................................................................................................................................... 3
4.1 基本原则 ........................................................................................................................................... 3
4.1.1 RTL
级代码风格
........................................................................................................................ 3
4.1.2
组合时序电路分开原则
........................................................................................................... 4
4.1.3
复位
........................................................................................................................................... 5
4.2 命名规则 ........................................................................................................................................... 5
4.2.1
基本命名标准
........................................................................................................................... 5
4.2.2
命名准则
................................................................................................................................... 5
4.3 VERILOG HDL源代码文件结构 .................................................................................................... 8
4.3.1 VERILOG HDL
代码文件文件头
........................................................................................... 8
4.3.2 VERILOG HDL
代码文件宏定义
......................................................................................... 10
4.3.3 VERILOG HDL
代码文件模块名及端口信号
..................................................................... 10
4.3.4 VERILOG HDL
代码文件信号、变量及参数
..................................................................... 10
4.3.5 VERILOG HDL
代码文件设计主体
...................................................................................... 11
4.3.6 VERILOG HDL
代码文件注释行
......................................................................................... 14
4.3.7 VERILOG HDL
代码文件独立
Include.v............................................................................... 14
5 VERILOG HDL代码范例 .................................................................................................................... 14
5.1 复用器表达方式 ............................................................................................................................. 14
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