mini-LVDS Specification
Version 0.1
2001 Texas Instruments Page 4 of 22
Confidential
3.0 Overview
Mini-LVDS is a uni-directional interface from the timing controller to the column drivers.
Topologically, it is a dual bus, with the buses carrying video data for the left and the right halves of the
panel, respectively. These buses are subsequently referred to as RLV and LLV for the right half and the
left half respectively. (Figure 3.1)
Physically, each bus consists of a number of pairs of transmission lines on a printed circuit board, with
each pair carrying differential serialized video and control information. The number of signal pairs is
left to implementation, and will be determined primarily by the maximum frequency that the column
driver semiconductor technology can support. The individual pairs making up XLV (X is either R or L)
are called XLVi, with ‘i’ ranging from 0 to n for a bus consisting of n+1 data pairs. The two lines
constituting the pair XLVi are XLViP and XLViM with the P and M designating the positive and the
negative lines of the pair. XLVi is deemed to be at a logic HIGH (logic state = 1) if the voltage on
XLViP is more than the voltage on XLViM.
RLV and LLV each also include clocks, which, like data signals, are differential pairs. To minimize
EMI without increasing receiver complexity drastically, data transfer occurs on both rising and falling
edges of the clock, i.e. the clock frequency is half of the maximum data transfer rate. The clock pairs
will be referred to as XLVCLK (X is either R or L), and the individual lines making up the pair will be
referred to as XLVCLKP and XLVCLKM. (Figure 3.2)
In addition to the differential pairs carrying video data, there are two more signals (TP1 and POL) that
make up mini-LVDS. These are CMOS level rail-to rail signals shared by both RLV and LLV. TP1 is
essentially a line delimiter, generated by the timing controller to signal end of data transfer every line.
POL controls the polarity of the driver outputs.
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