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Order Number: D51397-008, Rev. 2.4

Intel

Virtualization Technology for

Directed I/O

Architecture Specification

June 2016

Intel

Virtualization Technology for Directed I/O

Architecture Specification, Rev. 2.4 June 2016

2 Order Number: D51397-008

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.

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ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics

of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever

for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design

with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-

4725, or go to: http://www.intel.com/design/literature.htm

This document contains information on products in the design phase of development.

Intel

64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific

hardware and software you use. Consult your PC manufacturer for more information. For more information, visit http://www.intel.com/info/em64t

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, and virtual machine monitor (VMM). Functionality,

performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all

operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization

Legal Lines and Disclaimers

Intel and Itanium are trademarks of Intel Corporation in the U.S. and/or other countries.

*Other names and brands may be claimed as the property of others.

Intel

Virtualization Technology for Directed I/O

June 2016 Architecture Specification, Rev. 2.4

Order Number: D51397-008 3

Contents—Intel

Virtualization Technology for Directed I/O

Contents

1Introduction

1.1 Audience........................................................................................................ 1-1

1.2 Glossary ........................................................................................................ 1-2

1.3 References ..................................................................................................... 1-3

2Overview

2.1 Intel

Virtualization Technology Overview .......................................................... 2-1

2.2 VMM and Virtual Machines................................................................................ 2-1

2.3 Hardware Support for Processor Virtualization..................................................... 2-1

2.4 I/O Virtualization............................................................................................. 2-2

2.5 Intel

Virtualization Technology For Directed I/O Overview................................... 2-2

2.5.1 Hardware Support for DMA Remapping.....................................................2-3

2.5.1.1 OS Usages of DMA Remapping...................................................2-3

2.5.1.2 VMM Usages of DMA Remapping ................................................2-4

2.5.1.3 DMA Remapping Usages by Guests.............................................2-4

2.5.1.4 Interaction with Processor Virtualization......................................2-5

2.5.2 Hardware Support for Interrupt Remapping ..............................................2-6

2.5.2.1 Interrupt Isolation....................................................................2-6

2.5.2.2 Interrupt Migration...................................................................2-6

2.5.2.3 x2APIC Support.......................................................................2-6

2.5.3 Hardware Support for Interrupt Posting....................................................2-7

2.5.3.1 Interrupt Vector Scalability........................................................2-7

2.5.3.2 Interrupt Virtualization Efficiency ...............................................2-7

2.5.3.3 Virtual Interrupt Migration.........................................................2-7

3DMA Remapping

3.1 Types of DMA requests..................................................................................... 3-1

3.2 Domains and Address Translation...................................................................... 3-1

3.3 Remapping Hardware - Software View................................................................ 3-2

3.4 Mapping Devices to Domains ............................................................................ 3-2

3.4.1 Source Identifier ...................................................................................3-3

3.4.2 Root-Entry & Extended-Root-Entry ..........................................................3-3

3.4.3 Context-Entry.......................................................................................3-4

3.4.4 Extended-Context-Entry.........................................................................3-5

3.5 Hierarchical Translation Structures..................................................................... 3-7

3.6 First-Level Translation...................................................................................... 3-9

3.6.1 Translation Faults................................................................................3-11

3.6.2 Access Rights .....................................................................................3-11

3.6.3 Accessed, Extended Accessed, and Dirty Flags ........................................3-12

3.6.4 Snoop Behavior...................................................................................3-13

3.6.5 Memory Typing...................................................................................3-13

3.6.5.1 Selecting Memory Type from Page Attribute Table......................3-14

3.6.5.2 Selecting Memory Type from Memory Type Range Registers ........3-14

3.6.5.3 Selecting Effective Memory Type..............................................3-15

3.7 Second-Level Translation................................................................................ 3-16

3.7.1 Translation Faults................................................................................3-19

3.7.2 Access Rights .....................................................................................3-19

3.7.3 Snoop Behavior...................................................................................3-20

3.7.4 Memory Typing...................................................................................3-20

3.8 Nested Translation ........................................................................................ 3-21

3.8.1 Translation Faults................................................................................3-22

3.8.2 Access Rights .....................................................................................3-22

3.8.3 Snoop Behavior...................................................................................3-23

3.8.4 Memory Typing...................................................................................3-24

Intel

Virtualization Technology for Directed I/O—Contents

Intel

Virtualization Technology for Directed I/O

Architecture Specification, Rev. 2.4 June 2016

4 Order Number: D51397-008

3.9 Identifying Origination of DMA Requests ........................................................... 3-25

3.9.1 Devices Behind PCI-Express to PCI/PCI-X Bridges ....................................3-25

3.9.2 Devices Behind Conventional PCI Bridges................................................3-25

3.9.3 Root-Complex Integrated Devices..........................................................3-25

3.9.4 PCI-Express Devices Using Phantom Functions.........................................3-25

3.10 Handling Requests from Processor Graphics Device ............................................ 3-26

3.11 Handling Requests Crossing Page Boundaries .................................................... 3-26

3.12 Handling of Zero-Length Reads........................................................................ 3-26

3.13 Handling Requests to Interrupt Address Range .................................................. 3-27

3.14 Handling Requests to Reserved System Memory ................................................ 3-27

3.15 Root-Complex Peer to Peer Considerations........................................................ 3-28

4 Support For Device-TLBs

4.1 Device-TLB Operation...................................................................................... 4-1

4.1.1 Translation Request .............................................................................. 4-2

4.1.2 Translation Completion.......................................................................... 4-2

4.1.3 Translated Request............................................................................... 4-3

4.1.4 Invalidation Request & Completion.......................................................... 4-3

4.2 Remapping Hardware Handling of Device-TLBs ................................................... 4-4

4.2.1 Handling of ATS Protocol Errors .............................................................. 4-4

4.2.2 Root-Port Control of ATS Address Types................................................... 4-4

4.2.3 Handling of Translation Requests ............................................................ 4-4

4.2.3.1 Accessed, Extended Accessed, and Dirty Flags ............................ 4-8

4.2.3.2 Translation Requests for Multiple Translations ............................. 4-9

4.2.4 Handling of Translated Requests............................................................. 4-9

4.3 Handling of Device-TLB Invalidations................................................................ 4-10

5 Interrupt Remapping and Interrupt Posting

5.1 Interrupt Remapping....................................................................................... 5-1

5.1.1 Identifying Origination of Interrupt Requests............................................ 5-1

5.1.2 Interrupt Request Formats On Intel® 64 Platforms ................................... 5-2

5.1.2.1 Interrupt Requests in Compatibility Format................................. 5-2

5.1.2.2 Interrupt Requests in Remappable Format.................................. 5-3

5.1.3 Interrupt Remapping Table .................................................................... 5-4

5.1.4 Interrupt-Remapping Hardware Operation................................................ 5-4

5.1.4.1 Interrupt Remapping Fault Conditions ........................................ 5-6

5.1.5 Programming Interrupt Sources To Generate Remappable Interrupts........... 5-6

5.1.5.1 I/OxAPIC Programming............................................................ 5-7

5.1.5.2 MSI and MSI-X Register Programming........................................ 5-8

5.1.6 Remapping Hardware - Interrupt Programming......................................... 5-9

5.1.7 Programming in Intel

64 xAPIC Mode .................................................... 5-9

5.1.8 Programming in Intel

64 x2APIC Mode..................................................5-10

5.1.9 Handling of Platform Events ..................................................................5-10

5.2 Interrupt Posting ........................................................................................... 5-11

5.2.1 Interrupt Remapping Table Support for Interrupt Posting ..........................5-11

5.2.2 Posted Interrupt Descriptor...................................................................5-12

5.2.3 Interrupt-Posting Hardware Operation ....................................................5-12

5.2.4 Ordering Requirements for Interrupt Posting ...........................................5-13

5.2.5 Using Interrupt Posting for Virtual Interrupt Delivery ................................5-13

5.2.6 Interrupt Posting for Level Triggered Interrupts .......................................5-15

6 Caching Translation Information

6.1 Caching Mode................................................................................................. 6-1

6.2 Address Translation Caches.............................................................................. 6-1

6.2.1 Tagging of Cached Translations .............................................................. 6-2

6.2.2 Context-cache...................................................................................... 6-2

Intel

Virtualization Technology for Directed I/O

June 2016 Architecture Specification, Rev. 2.4

Order Number: D51397-008 5

Contents—Intel

Virtualization Technology for Directed I/O

6.2.2.1 Context-Entry Programming Considerations.................................6-4

6.2.3 PASID-cache ........................................................................................6-4

6.2.4 IOTLB..................................................................................................6-5

6.2.4.1 Details of IOTLB Use ................................................................6-6

6.2.4.2 Global Pages ...........................................................................6-7

6.2.5 Caches for Paging Structures ..................................................................6-7

6.2.5.1 PML4-cache ............................................................................6-8

6.2.5.2 PDPE-cache.............................................................................6-9

6.2.5.3 PDE-cache ............................................................................6-11

6.2.5.4 Details of Paging-Structure Cache Use ......................................6-12

6.2.6 Using the Paging-Structure Caches to Translate Requests.........................6-13

6.2.7 Multiple Cached Entries for a Single Paging-Structure Entry.......................6-14

6.3 Translation Caching at Endpoint Device ............................................................ 6-15

6.4 Interrupt Entry Cache .................................................................................... 6-15

6.5 Invalidation of Translation Caches ................................................................... 6-15

6.5.1 Register-based Invalidation Interface.....................................................6-16

6.5.1.1 Context Command Register.....................................................6-16

6.5.1.2 IOTLB Registers.....................................................................6-16

6.5.2 Queued Invalidation Interface...............................................................6-17

6.5.2.1 Context-cache Invalidate Descriptor.........................................6-19

6.5.2.2 PASID-cache Invalidate Descriptor ...........................................6-20

6.5.2.3 IOTLB Invalidate Descriptor.....................................................6-21

6.5.2.4 Extended IOTLB Invalidate Descriptor.......................................6-22

6.5.2.5 Device-TLB Invalidate Descriptor .............................................6-24

6.5.2.6 Extended Device-TLB Invalidate Descriptor................................ 6-25

6.5.2.7 Interrupt Entry Cache Invalidate Descriptor...............................6-26

6.5.2.8 Invalidation Wait Descriptor ....................................................6-27

6.5.2.9 Hardware Generation of Invalidation Completion Events..............6-27

6.5.2.10 Hardware Handling of Queued Invalidation Interface Errors ......... 6-28

6.5.2.11 Queued Invalidation Ordering Considerations............................. 6-29

6.5.3 IOTLB Invalidation Considerations .........................................................6-29

6.5.3.1 Implicit Invalidation on Page Requests......................................6-29

6.5.3.2 Caching Fractured Translations................................................6-30

6.5.3.3 Recommended Invalidation .....................................................6-30

6.5.3.4 Optional Invalidation..............................................................6-31

6.5.3.5 Delayed Invalidation ..............................................................6-32

6.5.4 TLB Shootdown Optimization for Root-Complex Integrated Devices............6-32

6.5.4.1 Deferred Invalidation..............................................................6-33

6.5.4.2 PASID-State Table .................................................................6-34

6.5.4.3 Remapping Hardware Handling of PASID State-Update Requests..6-35

6.5.4.4 Root-Complex Integrated Device Handling of PASID State-Update

Responses ............................................................................6-35

6.5.4.5 Ordering of PASID State-Update Requests and Responses ........... 6-36

6.5.4.6 Example TLB Shootdown using Deferred Invalidations.................6-36

6.5.5 Draining of Requests to Memory............................................................6-36

6.5.6 Interrupt Draining ...............................................................................6-37

6.6 Set Root Table Pointer Operation..................................................................... 6-38

6.7 Set Interrupt Remapping Table Pointer Operation .............................................. 6-38

6.8 Write Buffer Flushing ..................................................................................... 6-39

6.9 Hardware Register Programming Considerations................................................ 6-39

6.10 Sharing Remapping Structures Across Hardware Units........................................ 6-39

7 Translation Faults

7.1 Interrupt Translation Faults .............................................................................. 7-1

7.2 Address Translation Faults................................................................................ 7-1

7.2.1 Non-Recoverable Address Translation Faults .............................................7-2

7.2.1.1 Non-Recoverable Faults for Untranslated Requests Without PASID..7-2

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