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1
AMD I/O Virtualization Technology (IOMMU) Specification
48882—Rev 3.00—December 2016
Specification Agreement
This Specification Agreement (this “Agreement”) is a legal agreement between Advanced Micro
Devices, Inc. (“AMD”) and “You” as the recipient of the attached AMD Specification (the “Specifi-
cation”). If you are accessing the Specification as part of your performance of work for another party,
you acknowledge that you have authority to bind such party to the terms and conditions of this Agree-
ment. If you accessed the Specification by any means or otherwise use or provide Feedback (defined
below) on the Specification, You agree to the terms and conditions set forth in this Agreement. If You
do not agree to the terms and conditions set forth in this Agreement, you are not licensed to use the
Specification; do not use, access or provide Feedback about the Specification.
In consideration of Your use or access of the Specification (in whole or in part), the receipt and suffi-
ciency of which are acknowledged, You agree as follows:
1. You may review the Specification only (a) as a reference to assist You in planning and designing
Your product, service or technology (“Product”) to interface with an AMD product in compliance
with the requirements as set forth in the Specification and (b) to provide Feedback about the informa-
tion disclosed in the Specification to AMD.
2. Except as expressly set forth in Paragraph 1, all rights in and to the Specification are retained by
AMD. This Agreement does not give You any rights under any AMD patents, copyrights, trademarks
or other intellectual property rights. You may not (i) duplicate any part of the Specification; (ii)
remove this Agreement or any notices from the Specification, or (iii) give any part of the Specifica-
tion, or assign or otherwise provide Your rights under this Agreement, to anyone else.
3. The Specification may contain preliminary information, errors, or inaccuracies, or may not include
certain necessary information. Additionally, AMD reserves the right to discontinue or make changes
to the Specification and its products at any time without notice. The Specification is provided entirely
“AS IS.” AMD MAKES NO WARRANTY OF ANY KIND AND DISCLAIMS ALL EXPRESS,
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WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-
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5. You have no obligation to give AMD any suggestions, comments or feedback (“Feedback”) relat-
ing to the Specification. However, any Feedback You voluntarily provide may be used by AMD with-
out restriction, fee or obligation of confidentiality. Accordingly, if You do give AMD Feedback on

2
48882—Rev 3.00—December 2016
AMD I/O Virtualization Technology (IOMMU) Specification
any version of the Specification, You agree AMD may freely use, reproduce, license, distribute, and
otherwise commercialize Your Feedback in any product, as well as has the right to sublicense third
parties to do the same. Further, You will not give AMD any Feedback that You may have reason to
believe is (i) subject to any patent, copyright or other intellectual property claim or right of any third
party; or (ii) subject to license terms which seek to require any product or intellectual property incor-
porating or derived from Feedback or any Product or other AMD intellectual property to be licensed
to or otherwise provided to any third party.
6. You shall adhere to all applicable U.S., European, and other export laws, including but not limited
to the U.S. Export Administration Regulations (“EAR”), (15 C.F.R. Sections 730 through 774), and
E.U. Council Regulation (EC) No 428/2009 of 5 May 2009. Further, pursuant to Section 740.6 of the
EAR, You hereby certifies that, except pursuant to a license granted by the United States Department
of Commerce Bureau of Industry and Security or as otherwise permitted pursuant to a License Excep-
tion under the U.S. Export Administration Regulations ("EAR"), You will not (1) export, re-export or
release to a national of a country in Country Groups D:1, E:1 or E:2 any restricted technology, soft-
ware, or source code You receive hereunder, or (2) export to Country Groups D:1, E:1 or E:2 the
direct product of such technology or software, if such foreign produced direct product is subject to
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1 to Part 774 of EAR). For the most current Country Group listings, or for additional information
about the EAR or Your obligations under those regulations, please refer to the U.S. Bureau of Indus-
try and Security’s website at http://www.bis.doc.gov/.
7. If You are a part of the U.S. Government, then the Specification is provided with “RESTRICTED
RIGHTS” as set forth in subparagraphs (c) (1) and (2) of the Commercial Computer Software-
Restricted Rights clause at FAR 52.227-14 or subparagraph (c) (1)(ii) of the Rights in Technical Data
and Computer Software clause at DFARS 252.277-7013, as applicable.
8. This Agreement is governed by the laws of the State of California without regard to its choice of
law principles. Any dispute involving it must be brought in a court having jurisdiction of such dispute
in Santa Clara County, California, and You waive any defenses and rights allowing the dispute to be
litigated elsewhere. If any part of this agreement is unenforceable, it will be considered modified to
the extent necessary to make it enforceable, and the remainder shall continue in effect. The failure of
AMD to enforce any rights granted hereunder or to take action against You in the event of any breach
hereunder shall not be deemed a waiver by AMD as to subsequent enforcement of rights or subse-
quent actions in the event of future breaches. This Agreement is the entire agreement between You
and AMD concerning the Specification; it may be changed only by a written document signed by
both You and an authorized representative of AMD.

AMD I/O Virtualization Technology
(IOMMU) Specification
Publication # 48882 Revision: 3.00
Issue Date: December 2016

© 2011 – 2016 Advanced Micro Devices Inc. All rights reserved.
The information contained herein is for informational purposes only, and is subject to change without notice. While every
precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and
typographical errors, and AMD is under no obligation to update or otherwise correct this information. Advanced Micro
Devices, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document, and assumes no liability of any kind, including the implied warranties of noninfringement, merchantability or
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the parties or in AMD's Standard Terms and Conditions of Sale.
Trademarks
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names used in this publication are for identification purposes only and may be trademarks of their respective companies.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium
Reverse engineering or disassembly is prohibited.
PCI Express, PCIe and PCI-X are registered trademarks of PCI-Special Interest Group (PCI-SIG).
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5
AMD I/O Virtualization Technology (IOMMU) Specification
48882—Rev 3.00—December 2016
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1 IOMMU Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1 Summary of IOMMU Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2 Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.1 Replacing the GART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.2 Replacing the Device Exclusion Vector Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.2.3 32-bit to 64-bit Legacy I/O Device Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.2.4 User Mode Device Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2.5 Virtual Machine Guest Access to Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2.6 Virtualizing the IOMMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.2.7 Virtualized User Mode Device Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3 IOMMU Optional Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.1 Two-level Translation for Guest and Host Address Spaces . . . . . . . . . . . . . . . . . . . . 36
1.3.2 Enhanced Processor Page Table Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3.3 Performance Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3.4 Address Translation Services for Guest Virtual Addresses. . . . . . . . . . . . . . . . . . . . . 40
1.3.5 Peripheral Page Request Support Compatible with PCI-SIG PRI. . . . . . . . . . . . . . . . 41
1.3.6 Selecting Translation Tables in a Memory Transaction . . . . . . . . . . . . . . . . . . . . . . . 41
1.3.7 AMD64 Interrupt Virtualization (Guest Virtual APIC Interrupt Controller) . . . . . . . 41
1.3.8 Enhanced Support for Access and Dirty Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.3.9 Guest I/O Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.3.10 SMI Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.3.11 Hardware Error Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1.2 IOMMU Logical Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.3 IOMMU Event Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.4 Special Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.1.5 System Management Interrupt (SMI) Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.2 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.2.1 Updating Shared Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.2 Device Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.3 I/O Page Tables for Host Translations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.2.4 Sharing AMD64 Processor and IOMMU Page Tables—GPA-to-SPA. . . . . . . . . . . . 80
2.2.5 Interrupt Remapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.2.6 I/O Page Tables for Guest Translations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.2.7 Guest and Nested Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.2.8 Guest Virtual APIC Table for Interrupt Virtualization . . . . . . . . . . . . . . . . . . . . . . . 109
2.2.9
Guest I/O Pr
otection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.3 Starting the IOMMU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.3.1 Data Structure Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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