TC358748XBG/TC358746AXBGdatasheet

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TC358746AXBG/TC358748XBG

1 / 19 2017-10-11

Rev.1.6a

Toshiba Electronic Devices & Storage Corporation

CMOS Digital Integrated Circuit Silicon Monolithic

TC358746AXBG/TC358748XBG

Mobile Peripheral Devices

Overview

The MIPI

CSI-2 to Parallel port and Parallel port to CSI-2

(TC358746AXBG/TC358748XBG) is a bridge device that converts

MIPI data transfers from devices such as a camera to an application

processor over a Parallel port interface. All internal registers can be

access through I

C or SPI (in CSI out case only).

Features

● CSI-2 TX/RX Interface

 MIPI CSI-2 compliant (Version 1.01 Revision

0.04 – 2 April 2009)

 Configurable to TX or RX controller

 Supports up to 1Gbps per data lane

 Supports up to 4 data lanes

 Supports video data formats

- RX: RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-

bit), RGB888/666/565 and User-Defined 8-bit

- TX: YUV422 (CCIR/ITU 8/10-bit), YUV444,

RGB888/666/565 and RAW8/10/12/14

● Parallel Port Interface

 Supports data formats

- 24-bit bus – un-packed format (Both Input and

Output mode)

 RGB888/666/565, RAW8/10/12/14 and

YUV422 8-bit (on 8/16-bit data bus) and 10-bit

data formats.

 YUV444 (Parallel Input mode only)

- YUV422 8-bit – ITU BT.656 and ITU BT.601

(Parallel input mode only)

 Up to 100 MHz PCLK frequency for Output

mode, and 166 MHz for Input mode.

● I

C Slave Interface (CS = L)

 Support for normal (100 kHz), fast mode (400

kHz) and special mode (1 MHz)

 Configure all TC358746AXBG/TC358748XBG

internal registers

● SPI Slave Interface (Only applicable in CSIOut

configuration, MSEL = H, and CS = H)

 SPI interface support for up to 25 MHz

operation.

 Configure all TC358746AXBG/TC358748XBG

internal registers

● GPIO signals

 3 GPIO signals

- Three GPIO signals can be configured as

control signals (MCLK, CXRST, XShutdown) for

CSI-2 RX device.

- Or one GPIO signal can be configured as INT

signal for Parallel interface.

● System

 Clock and power management support to

achieve low power states.

● Power supply inputs

 Core and MIPI D-PHY: 1.2 V

 I/O: 1.8 V – 3.3 V

P-VFBGA72-0404-0.40A3

Weight:

32 mg (Typ.)

Weight: 68 mg (Typ.)

P-VFBGA80-0707-0.65-001

TC358746AXBG

TC358748XBG

TC358746AXBG/TC358748XBG

2 / 19 2017-10-11

Table of content

REFERENCES ..................................................................................................................................................... 5

1. Overview .......................................................................................................................................................... 6

2. Features ........................................................................................................................................................... 8

2.1. Typical Power Consumption ...................................................................................................................... 9

3. External Pins .................................................................................................................................................. 10

3.1. TC358746AXBG pinout description ........................................................................................................ 10

3.2. TC358746AXBG BGA72 pin Count Summary ........................................................................................ 11

3.3. TC358748XBG BGA80 Pin Count Summary .......................................................................................... 11

3.4. TC358746AXBG Pin Layout .................................................................................................................... 12

3.5. TC358748XBG Pin Layout ...................................................................................................................... 13

4. Package ......................................................................................................................................................... 14

4.1. TC358746AXBG Package ....................................................................................................................... 14

4.2. TC358748XBG Package ......................................................................................................................... 15

5. Electrical Characteristics ................................................................................................................................ 16

5.1. Absolute Maximum Ratings ..................................................................................................................... 16

5.2. Operating Condition................................................................................................................................. 16

5.3. DC Electrical Specification ...................................................................................................................... 17

6. Revision History ............................................................................................................................................. 18

RESTRICTIONS ON PRODUCT USE ............................................................................................................... 19

Table of Figures

Figure 1.1 System Overview with TC358746AXBG/TC358748XBG in CSI-2 RX to Parallel Port

Configuration ......................................................................................................................................... 6

Figure 1.2 System Overview with TC358746AXBG/TC358748XBG in Parallel Port to CSI-2 TX

Configuration ......................................................................................................................................... 7

Figure 3.1 TC358746AXBG BGA72-Pin Layout (Top View) ................................................................... 12

Figure 3.2 TC358748XBG 80-Pin Layout (Top View).............................................................................. 13

Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package ........................................................... 14

Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 package ........................................................... 15

List of Tables

Table 3.1 TC358746AXBG/ TC358748XBG Functional Signal List ........................................................ 10

Table 3.2 TC358746AXBG BGA 72Pin Count Summary ........................................................................ 11

Table 3.3 TC358748XBG BGA 80 Pin Count Summary ......................................................................... 11

Table 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension...................................... 14

Table 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension ..................................... 15

Table 6.1 Revision History ....................................................................................................................... 18

TC358746AXBG/TC358748XBG

4 / 19 2017-10-11

1 NOTICE OF DISCLAIMER

2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled

3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on

4 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS

5 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all

6 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if

7 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of

8 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of

9 negligence.

10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished,

11 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express

12 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related

13 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and

14 cannot be used without its express prior written permission.

15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET

16 POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD

17 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY

18 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR

19 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE

20 GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,

21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER

22 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR

23 ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,

24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH

25 DAMAGES.

26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is

27 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the

28 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;

29 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance

30 with the contents of this Document. The use or implementation of the contents of this Document may

31 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,

32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI

33 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any

34 IPR or claims of IPR as respects the contents of this Document or otherwise.

35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

36 MIPI Alliance, Inc.

37 c/o IEEE-ISTO

38 445 Hoes Lane

39 Piscataway, NJ 08854

40 Attn: Board Secretary

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