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CUSTOMER EDUCATION SERVICES

IC Compiler 1

Workshop

Student Guide

20-I-071-SSG-008 2008.09

Synopsys Customer Education Services

700 East Middlefield Road

Mountain View, California 94043

Workshop Registration: 1-800-793-3448

www.synopsys.com

Synopsys Customer Education Services

proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a

license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the

software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic,

mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by

the license agreement.

Destination Control Statement

All technical data contained in this publication is subject to the export control laws of the United States of America.

Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to

determine the applicable regulations and to comply with them.

Disclaimer

SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH

REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

Registered Trademarks (®)

Synopsys, AMPS, Cadabra, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM,

HSPICE, iN-Phase, in-Sync, Leda, MAST, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler,

PrimeTime, SiVL, SNUG, SolvNet, System Compiler, TetraMAX, VCS, Vera, and YIELDirector are registered trademarks

of Synopsys, Inc.

Trademarks (™)

AFGen, Apollo, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, Columbia,Columbia-CE, Cosmos, CosmosEnterprise,

CosmosLE, CosmosScope, CosmosSE, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision,

DesignerHDL, Direct Silicon Access, Discovery, Encore, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical

Optimization Technology, HSIMplus, HSPICE-Link, iN-Tandem, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT,

JupiterXT-ASIC, Liberty, Libra-Passport,Library Compiler, Magellan, Mars, Mars-Rail, Milkyway, ModelSource, Module

Compiler, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Raphael-NES,Saturn, Scirocco, Scirocco-i, Star-RCXT,

Star-SimXT, Taurus, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are trademarks of Synopsys,

Inc.

Service Marks (

)

MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered

trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license.

All other product or company names may be trademarks of their respective owners.

Document Order Number: 20-I-071-SSG-008

IC Compiler 1 Student Guide

Table of Contents

Synopsys 20-I-071-SSG-008 i IC Compiler 1

Unit i: Introduction & Overview

Facilities ............................................................................................................................ i-2

Workshop Goal ................................................................................................................. i-3

Target Audience ................................................................................................................ i-4

Workshop Prerequisites .................................................................................................... i-5

Introductions ..................................................................................................................... i-6

Curriculum Flow ............................................................................................................... i-7

Agenda .............................................................................................................................. i-8

Agenda .............................................................................................................................. i-9

Agenda ............................................................................................................................ i-10

High-Level IC Compiler Flow ........................................................................................ i-11

Lab 0: IC Compiler GUI – MainWindow ....................................................................... i-12

Lab 0: IC Compiler GUI – LayoutWindow .................................................................... i-13

Lab 0A: IC Compiler GUI .............................................................................................. i-14

Unit 1: Data Setup & Basic Flow

Unit Objectives ................................................................................................................ 1-2

A Word of Caution About Scripts and Flows .................................................................. 1-3

General IC Compiler Flow ............................................................................................... 1-4

Data Setup ........................................................................................................................ 1-5

Logical Libraries .............................................................................................................. 1-6

Physical Reference Libraries ........................................................................................... 1-7

Milkyway Structure of Physical Libraries ....................................................................... 1-8

Specify the Logical Libraries ........................................................................................... 1-9

Define ‘logic0’ and ‘logic1’ ........................................................................................... 1-10

IC Compiler Initialization Files ..................................................................................... 1-11

Create a “Container”: The Design Library .................................................................... 1-12

Initial Structure of a Milkyway Design Library ............................................................ 1-13

The Technology File (.tf file) ......................................................................................... 1-14

Example of a Technology File ...................................................................................... 1-15

The check_library Command ......................................................................................... 1-16

Specify TLU+ Parasitic RC Model Files ....................................................................... 1-17

Timing is Based on Cell and Net Delays ....................................................................... 1-18

TLU+ Models ................................................................................................................ 1-19

Mapping file ................................................................................................................... 1-20

Read the Netlist and Create a Design CEL .................................................................... 1-21

Must Uniquify Multiply Instantiated Designs ............................................................... 1-22

Linking: Resolving References ...................................................................................... 1-23

Milkyway Design Library with Design Cell .................................................................. 1-24

Shortcut: Import the Netlist ........................................................................................... 1-25

Verify Logical Libraries Are Loaded ............................................................................ 1-26

Define Logical Power/Ground Connections .................................................................. 1-27

Apply and Check Timing Constraints ............................................................................ 1-28

Table of Contents

Synopsys 20-I-071-SSG-008 ii IC Compiler 1

Timing Constraints......................................................................................................... 1-29

Ensure Proper Modeling of Clock Tree ......................................................................... 1-30

Test for Understanding .................................................................................................. 1-31

Apply Timing and Optimization Controls ..................................................................... 1-32

Available Timing and Optimization Controls ................................................................ 1-33

Timing and Optimization Setup Example ...................................................................... 1-34

Enable Multiple Clocks per Register ............................................................................. 1-35

Enable Constant Propagation ......................................................................................... 1-36

Enable Multiple Port Net Buffering ............................................................................... 1-37

Enable Constant Net Buffering, if Needed .................................................................... 1-38

Apply Timing Derating for On-Chip Variation ............................................................. 1-39

Define “Don’t Use” or “Preferred” Cells ....................................................................... 1-40

Keep Spare or Unloaded Cells ....................................................................................... 1-41

Apply Area Constraint for Area Recovery .................................................................... 1-42

Apply a Power and Area Critical Range ........................................................................ 1-43

IC Compiler Organizes Paths into Groups ..................................................................... 1-44

General Problem: Sub-Critical Paths Ignored................................................................ 1-45

Serious Problem: Reg-to-Reg Paths Ignored ................................................................ 1-46

Solution: User-Defined Path Groups ............................................................................. 1-47

Define Path Groups for I/O Paths, if needed ................................................................. 1-48

Prevent Buffering of Clock-as-Data Networks .............................................................. 1-49

Modify Optimization Priority if Needed........................................................................ 1-50

Enable Recovery and Removal Timing Arcs ................................................................. 1-51

Perform a ‘Timing Sanity Check’ .................................................................................. 1-52

Remove Unwanted “Ideal Net/Networks” ..................................................................... 1-53

Save the Design .............................................................................................................. 1-54

Design Library with New Design Cell ........................................................................... 1-55

UNIX Manipulation of a Milkyway Database ............................................................... 1-56

Restoring Variables ........................................................................................................ 1-57

Restoring Logical Library and TLU+ Settings .............................................................. 1-58

Loading an Existing Cell After Exiting ICC .................................................................. 1-59

Data Setup Summary ..................................................................................................... 1-60

Data Setup Example (1 of 3) .......................................................................................... 1-61

Data Setup Example (2 of 3) .......................................................................................... 1-62

Data Setup Example (3 of 3) .......................................................................................... 1-63

Test for Understanding (1 of 2) ..................................................................................... 1-64

Test for Understanding (2 of 2) ..................................................................................... 1-65

General IC Compiler Flow ............................................................................................. 1-66

Design Planning ............................................................................................................. 1-67

Load an Existing Floorplan ............................................................................................ 1-68

Placement and Related Optimizations ........................................................................... 1-69

Clock Tree Synthesis ..................................................................................................... 1-70

Routing ........................................................................................................................... 1-71

Chip Finishing ................................................................................................................ 1-72

Analyzing the Results (1/2) ........................................................................................... 1-73

Analyzing the Results (2/2) ........................................................................................... 1-74

Table of Contents

Synopsys 20-I-071-SSG-008 iii IC Compiler 1

Example “run” Script ..................................................................................................... 1-75

Basic Flow Summary ..................................................................................................... 1-76

Lab 1: Design Setup and Basic Flow ............................................................................. 1-77

Unit 2: Design Planning

Unit Objectives ................................................................................................................ 2-2

General IC Compiler Flow ............................................................................................... 2-3

Terminology ..................................................................................................................... 2-4

ICC Design Planning and Re-Synthesis Flow ................................................................. 2-5

Select the Design Planning Task GUI ............................................................................. 2-6

Create the Starting Floorplan ........................................................................................... 2-7

Create Physical-only Pad Cells ........................................................................................ 2-8

Specify Pad Cell Locations .............................................................................................. 2-9

Initialize the Floorplan ................................................................................................... 2-10

Core Area Parameters .................................................................................................... 2-11

Floorplan After Initialization ......................................................................................... 2-12

Insert Pad Filler Cells..................................................................................................... 2-13

Create P/G Pad Rings..................................................................................................... 2-14

Prior to Virtual Flat Placement ...................................................................................... 2-15

Ignore Extra Routing Layers .......................................................................................... 2-16

Constraining Macros ...................................................................................................... 2-17

Manual Macro Placement .............................................................................................. 2-18

Macro Constraints: Arrays ............................................................................................. 2-19

Macro Constraints: Legal Orientation Option .............................................................. 2-20

Macro Constraints: Anchor Bound Option ................................................................... 2-21

Macro Constraints: Side Channel Option ..................................................................... 2-22

Macro Constraints: Relative Location ........................................................................... 2-23

Congestion Potential Around Macro Cells .................................................................... 2-24

Apply Global Placement Blockages .............................................................................. 2-25

Apply Specific Placement Blockages ............................................................................ 2-26

Summary: Create the Starting Floorplan ....................................................................... 2-27

Test For Understanding.................................................................................................. 2-28

Perform Virtual Flat Placement ..................................................................................... 2-29

Set Placement Strategy Parameters ................................................................................ 2-30

VF Placement with Virtual IPO (VIPO) ........................................................................ 2-31

Perform Virtual Flat Placement ..................................................................................... 2-32

Hierarchy Aware Placement or Gravity ......................................................................... 2-33

Summary: Virtual Flat Placement .................................................................................. 2-34

Reduce Congestion ........................................................................................................ 2-35

Is the Design Congested? ............................................................................................... 2-36

Understanding the Congestion Calculation ................................................................... 2-37

Congestion Guidelines ................................................................................................... 2-38

Modify Macro Placement Constraints ........................................................................... 2-39

Apply Standard Cell Placement Constraints .................................................................. 2-40

Is High Cell Density Causing Congestion? ................................................................... 2-41

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