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Trade-Offs in Analog
Circuit Design
The Designer’s Companion
Edited by
Chris Toumazou
Imperial College, UK
George Moschytz
ETH-Zentrum, Switzerland
and
Barrie Gilbert
Analog Devices, USA
Editing Assistance
Ganesh Kathiresan
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47673-8
Print ISBN: 1-4020-7037-3
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstore at: http://ebooks.kluweronline.com
Dordrecht

Contents
Foreword
List of Contributors
xxiii
xxix
Design Methodology
Intuitive Analog Circuit Design
Chris Toumazou
Mass-Production of Microdevices
2.1.1 Present Objectives
Unique Challenges of Analog Design
2.2.1 Analog is Newtonian
Designing with Manufacture in Mind
2.3.1 Conflicts and Compromises
2.3.2 Coping with Sensitivities: DAPs, TAPs and STMs
Robustness, Optimization and Trade-Offs
2.4.1 Choice of Architecture
2.4.2 Choice of Technology and Topology
2.4.3 Remedies for Non-Robust Practices
2.4.4 Turning the Tables on a Non-Robust Circuit: A Case Study
Holistic optimization of the LNA
A further example of biasing synergy
2.4.5 Robustness in Voltage References
2.4.6 The Cost of Robustness
Toward Design Mastery
2.5.1 First, the Finale
2.5.2 Consider All Deliverables
2.5.3 Design Compression
2.5.4 Fundamentals before Finesse
2.5.5 Re-Utilization of Proven Cells
2.5.6 Try to Break Your Circuits
2.5.7 Use Corner Modeling Judiciously
2.5.8 Use Large-Signal Time-Domain Methods
2.5.9 Use Back-Annotation of Parasitics
2.5.10 Make Your Intentions Clear
2.5.11 Dubious Value of Check Lists
2.5.12 Use the “Ten Things That Will Fail” Test
Conclusion
1
1
2
6
7
7
9
Design for Manufacture
Barrie Gilbert
1
1.1
1.2
Introduction
The Analog Dilemma
References
2
2.1
2.2
2.3
2.4
2.5
2.6
11
13
14
15
16
22
25
27
32
34
39
44
50
54
55
56
57
58
61
62
63
64
68
68
69
70
72
73
v

vi
Contents
General Performance
3
Trade-Offs in CMOS VLSI Circuits
Andrey V. Mezhiba and Eby G. Friedman
75
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Area
Speed
Power
Design Productivity
Testability
Reliability
Noise Tolerance
Packaging
General Considerations
Power dissipation in CMOS VLSI circuits
Technology scaling
VLSI design methodologies
Structural Level
3.3.1 Parallel Architecture
3.3.2 Pipelining
Circuit Level
3.4.1 Static versus Dynamic
3.4.2 Transistor Sizing
3.4.3 Tapered Buffers
Physical Level
Process Level
3.6.1 Scaling
3.6.2 Threshold Voltage
3.6.3 Power Supply
3.6.4 Improved Interconnect and Dielectric Materials
Future Trends
75
78
78
79
79
80
81
81
82
83
83
84
85
86
86
87
88
89
90
91
95
99
102
103
103
103
104
104
107
108
115
115
115
116
116
117
117
118
118
119
Glossary
References
4
Floating-gate Circuits and Systems
Tor Sverre Lande
4.1
4.2
4.3
UV-conductance
Fowler–Nordheim Tunneling
Hot Carrier Injection
Introduction
Design Criteria
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
Introduction
Device Physics
4.2.1
4.2.2
4.2.3
Programming
4.3.1
4.3.2
4.3.3

Contents
vii
4.4
4.5
4.6
4.7
Circuit Elements
4.4.1 Programming Circuits
Inter-poly tunneling
Example: Floating-gate on-chip knobs
Inter-poly UV-programming
MOS-transistor UV-conductance
Example: MOS transistor threshold tuning
Combined programming techniques
Example: Single transistor synapse
High-voltage drivers
FGMOS Circuits and Systems
4.5.1 Autozero Floating-Gate Amplifier
4.5.2 Low-power/Low-voltage Rail-to-Rail Circuits Using FGUVMOS
Digital FGUVMOS circuits
Low-voltage rail-to-rail FGUVMOS amplifier
4.5.3 Adaptive Retina
4.5.4 Other Circuits
Retention
Concluding Remarks
References
5
119
120
120
121
121
122
123
124
126
127
128
128
130
130
130
132
134
134
134
135
139
139
140
140
141
142
143
144
146
147
148
150
151
152
153
155
155
156
157
157
159
163
164
Bandgap Reference Design
Arie van Staveren, Michiel H. L. Kouwenhoven, Wouter A. Serdijn and Chris
J. M. Verhoeven
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Introduction
The Basic Function
Temperature Behavior of
General Temperature Compensation
A Linear Combination of Base–Emitter Voltages
5.5.1 First-Order Compensation
5.5.2 Second-Order Compensation
The Key Parameters
Temperature-Dependent Resistors
Noise
5.8.1 Noise of the Idealized Bandgap Reference
5.8.2 Noise of a First-Order Compensated Reference
5.8.3 Noise of a Second-Order Compensated Reference
5.8.4 Power-Supply Rejection
Simplified Structures
5.9.1 First-Order Compensated Reference
5.9.2 Second-Order Compensated Reference
Design Example
5.10.1 First-Order Compensated Bandgap Reference
5.10.2 Second-Order Compensated Bandgap Reference
Conclusions
References
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