1. Timing Analysis Introduction
Comprehensive timing analysis of your design allows you to validate circuit
performance, identify timing violations, and drive the Fitter's placement of logic to
meet your timing goals. The Intel
®
Quartus
®
Prime Timing Analyzer uses industry-
standard constraint and analysis methodology to report on all data required times,
data arrival times, and clock arrival times for all register-to-register, I/O, and
asynchronous reset paths in your design.
The Timing Analyzer verifies that required timing relationships are met for your design
to correctly function, and confirms actual signal arrival times against the constraints
that you specify. This use guide provides an introduction to basic timing analysis
concepts, along with step-by-step instructions for using the Intel Quartus Prime
Timing Analyzer.
1.1. Timing Analysis Basic Concepts
This user guide introduces the following concepts to describe timing analysis:
Table 1. Timing Analyzer Terminology
Term Definition
Arrival time The Timing Analyzer calculates the data and clock arrival time versus the required time
at register pins.
Cell Device resource that contains look-up tables (LUT), registers, digital signal processing
(DSP) blocks, memory blocks, or input/output elements. In Intel Stratix
®
series
devices, the LUTs and registers are contained in logic elements (LE) modeled as cells.
Clock Named signal representing clock domains inside or outside of your design.
Clock-as-data analysis More accurate timing analysis for complex paths that includes any phase shift
associated with a PLL for the clock path, and considers any related phase shift for the
data path.
Clock hold time Minimum time interval that a signal must be stable on the input pin that feeds a data
input or clock enable, after an active transition on the clock input.
Clock launch and latch edge The launch edge is the clock edge that sends data out of a register or other sequential
element, and acts as a source for the data transfer. The latch edge is the active clock
edge that captures data at the data port of a register or other sequential element,
acting as a destination for the data transfer.
Clock pessimism Clock pessimism refers to use of the maximum (rather than minimum) delay variation
associated with common clock paths during static timing analysis.
Clock setup Minimum time interval between the assertion of a signal at a data input, and the
assertion of a low-to-high transition on the clock input.
Net A collection of two or more interconnected components.
Node Represents a wire carrying a signal that travels between different logical components
in the design. Most basic timing netlist unit. Used to represent ports, pins, and
registers.
continued...
UG-20140 | 2018.09.24
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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