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The World Leader in High Performance Signal Processing Solutions
ADV7510 to ADV7511Dierences
September, 2010

Overview
Pin Out and other Hardware Changes
Audio Return Channel
3D Format Support
Improved Electrical Characteristics
CEC
3 Buffers
HDMI 1.4 CEC Features
HDCP
CSC and Packet Update Feature
Video Input Detection
Video Data Range Clipping
Miscellaneous
Chip ID and Revision Registers
TMDS Clock Inversion
Internal HPD Pulldown
Changes in Fixed Registers
2

Pinout Dierences
ADV7511 and ADV7510 share a “pin-similar” 100-pin LQFP package
HEAC+/- and SPDIF_OUT pins added
Changed from GND and NC
HPD pin now includes an internal pull-down resistor (see slide 24)
3
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
41
42
40
43
44
45
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
69
70
71
72
73
74
75
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
94
95
96
97
98
99
100
ADV7511
TOP VIEW
(Not to Scale)
46
47
48
49
50
GND
DDCSDA
DDCSCL
HEAC-
GND
GND
GND
GND
PV
DD
PV
DD
PV
DD
DV
DD
DV
DD
D18
D22
D21
D20
D19
D35
D29
D28
D27
D26
D25
D24
D23
D34
D33
D32
D31
D30
SCL
SDA
HEAC+
VSYNC
DSD0
DSD1
DSD_CLK
SPDIF
MCLK
I2S0
I2S3
I2S2
I2S1
SCLK
LRCLK
GND
GND
HSYNC
DE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
CLK
D17
DV
DD
DV
DD
CEC_CLK
DV
DD
CEC_IN
DV
DD
_3V
SPDIF_OUT
INT
GND
TX2+
TX2–
AV
DD
TX1+
TX1–
PD
GND
TX0+
TX0–
AV
DD
TXC+
TXC–
GND
HPD
AV
DD
R_EXT
GND
BGV
DD
DSD2
DSD5
DSD4
DSD3

Audio Return Channel
ADV7511 adds the ARC function from HDMI 1.4a
PCB Change
Add the following circuit to incorporate the ARC function in hardware
ARC Registers
4
SPDIF_OUT
ADV7511
HEAC+
52
HEAC
-
51
ARC Receiver
46
1uF
1uF
50 ohms
1.8V
From HDMI
connector
To SPDIF Receiver
(3.3V CMOS)

3D Format Support (1)
ADV7510 does not work with all 3D structures at all resolutions
ADV7511 works with all 3D structures at all video resolutions
defined in CEA 861E, assuming the TMDS clock is within the
allowable range for the ADV7511 (< 225 MHz)
Registers for DE Generation, Embedded Sync Generation, and
Sync Adjustment have been expanded in order to support all 3D
modes. This is shown in the following tables:
DE Generation
5
Parameter ADV7510 ADV7511
Hsync Delay 10 bit: (0x35[7:0],0x36[7:6]) 11 bit: (0xFB[7],0x35[7:0],0x36[7:6])
Vsync Delay 6 bit: (0x36[5:0]) 8 bit: (0xFB[6:5], 0x36[5:0]
Active Width 12 bit: (0x37[4:0],0x38[7:1]) 13 bit: (0xFB[4], 0x37[4:0],0x38[7:1])
Active Height 12 bit: (0x39[7:0],0x3A[7:4]) 13 bit: (0xFB[3], 0x39[7:0],0x3A[7:4])
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