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Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
M/B Schematics Document
REV:0.1
2012-11-07
GPU nVIDIA N14M-GL / N14P-GV2
File Name : NM-A043, NM-A044
Model Name : VILE1 & VILE2
BOM P/N:
VILE1:
VILE2:
Size Document Number Rev
Date: Sheet
of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Cover Page
Custom
1 59
Wednesday, November 07, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Cover Page
Custom
1 59
Wednesday, November 07, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Cover Page
Custom
1 59
Wednesday, November 07, 2012
2012/07/01
2014/07/01
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI Express
Mini card
Slot 2
WWAN/mSATA
USB
PCI Express
Mini card
Slot 1
WLAN/WiMAX/BT
PCI-E(WLAN)
USB(BT)
SIM Card
BIOS 8M+4M
S
PI ROM
USB PORT 3.0 x 2
37.5mm * 37.5mm
SATA ODD CONN
S
ATA3.0 HDD CONN
25mm*25mm
D
igital MIC
Intel
A
udio Codec
CX20671-21Z CODEC
CMOS Camera
LPC BUS
2
Channel Speaker
ENE KBC9012
Int.KBD
HD Audio
Click Pad
D
DR3-SO-DIMM X2
Dual Channel
EC
FCBGA 989
rPGA 989 Socket
Ivy Bridge
Intel
Panther Point
Audio combo Jack
Fintek F75303M
Thermal Sensor
G-Sensor
SATA
Track Point
HM76
Finger Printer
HDMI Connector
PCI-E X8
CRT Connector
LV
DS Connector
DDR3*4
nVIDIA N14M-GL
VRAM 256M*16/
12
8M*16/64M*16
Page 4~10
Pa
ge 13~21
Page 24~32
Page 11~12
Page 32
Page 32
Page 33
Page 34
Page 35
Page 36
Page 41
Page 39
Page 39
Page 39
Page 36
Page 36
Page 37
Page 40
Page 38
Page 35
Page 35
Page 35
Page 39
Page 39
Page 38
Page 38
Page 13
100MHz
5GB/s
DMI x4
100MHz
FDI x8
2.7GT/s
(UMA)
1.5V DDR3 1600MHz
Memory Bus
U
SB 2.0
SA
TA
LVDS
RGB
HDMI
PCI-E
SPI
USB 3.0
m-SATA CONN
Page 38
n
VIDIA N14P-GV2
Sub-Board
UPEK TCS5DA6C0
DDR3*4
V
RAM 256M*16/
128M*16/64M*16
TPM
Page 40
R
J45 CONN
RTL8111F(Giga)
Realtek
Realtek RTS5229
Card Reader
Page 40
P
age 40
Page 36
Sub-Board
cable
cable
DC-IN dongle
USB3+DP
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Block Diagram
Custom
2 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Block Diagram
Custom
2 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Block Diagram
Custom
2 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
X
V
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
XX
V
V
X
XX
PCH
Thermal
Sensor
X
X
X
SML0CLK
SML0DATA
PCH
SMB_EC_CK2
SOURCE
KB9012
VGA BATT KE9012 SODIMM
SMBUS Control Table
SMBCLK
SMBDATA
PCH
WLAN
WWAN
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
X V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
KB9012
SML1CLK
SML1DATA
PCH
XX X
X
X
V
Thermal Sensor Fintek F75303M
1001_101xb
USB3.0
USB 2.0 Port
3 External
USB Port
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
BOARD ID Table
EC SM Bus1 address
Device
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
STATE
SIGNAL
Full ON
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
PCH SM Bus address
Device A
ddress
Address Address
Voltage Rails
Unpop
BTO Item BOM Structure
ON
ON
ON
ON ON ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFFLOW LOW LOW LOW
LOWLOWLOW
LOW LOW
HIGH HIGH HIGH HIGH
HIGH
HIGH
HIGH
EC SM Bus2 address
Device
Smart Battery
0001 011X b
Connector ME@
@
+3VS
45 LEVEL 45@
FPR
Mini Card(WWAN)
+3VS
+3VS
+3VS
BOM Structure Table
O
X
S3
+3VS
X
X
+3VALW
+5VS
O
+CPU_CORE
OO
X
X X
+VCCP
power
plane
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.5V
V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
+3VS
O
+VCC_GFXCORE_AXG
+1.8VS
+0.75VS
+
1.05VS
+VGA_CORE
USB 3.0 Port (Left Side)
Mini Card(WLAN/BT)
USB Port (Right Side)
USB 3.0 Port (Left Side)
USB 3.0 Port
DIS@NVidia
UMA@
X76@VRAM Option
Intel UMA
Intel SBA SBA@
Intel AOAC AOAC@
TPM TPM@
GPU N14M-GL
GPU N14P-GV2
N14MGL@
N14PGV2@
+3VM
+1.05VM
O
O
O
M3 Supported
M3 Supported
M3 Supported
X
+3V_PCH@PCH AUX Power
Touch Panel
SSD@SSD
NM-A043
FP@
Touch@
Finger Print Board
Touch Panel
SIM Card Slot 3G@
0.2
Camera
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Notes List
Custom
3 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Notes List
Custom
3 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
Notes List
Custom
3 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
B2
46J_BARCODE_16X7
@
B2
46J_BARCODE_16X7
@
1
1
ZZZ5
DA PCB
DA80000TG00
ZZZ5
DA PCB
DA80000TG00
B3
UUID_BARCODE_16X7
@
B3
UUID_BARCODE_16X7
@
1
1
1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
PEG_ICOMPI and RCOMPO signals should be shorted and routed
w
ith - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
Nvidia support PCIE Gen2
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N1
PEG_COMP
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P1
PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N7
EDP_COMP
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
DMI_CTX_PRX_P015
DMI_CRX_PTX_P015
DMI_CTX_PRX_N115
DMI_CRX_PTX_N115
DMI_CTX_PRX_P315
DMI_CRX_PTX_P315
DMI_CTX_PRX_P215
DMI_CTX_PRX_N015
DMI_CRX_PTX_N315
DMI_CRX_PTX_P215
DMI_CTX_PRX_N315
DMI_CTX_PRX_P115
DMI_CRX_PTX_N015
DMI_CRX_PTX_N215
DMI_CRX_PTX_P115
DMI_CTX_PRX_N215
FDI_CTX_PRX_N015
FDI_CTX_PRX_N115
FDI_CTX_PRX_N215
FDI_CTX_PRX_N315
FDI_CTX_PRX_N415
FDI_CTX_PRX_N515
FDI_CTX_PRX_N615
FDI_CTX_PRX_N715
FDI_CTX_PRX_P015
FDI_CTX_PRX_P115
FDI_CTX_PRX_P215
FDI_CTX_PRX_P315
FDI_CTX_PRX_P415
FDI_CTX_PRX_P515
FDI_CTX_PRX_P615
FDI_CTX_PRX_P715
FDI_FSYNC015
FDI_FSYNC115
FDI_INT15
FDI_LSYNC015
FDI_LSYNC115
PCIE_CRX_GTX_N[0..7] 22
PCIE_CRX_GTX_P[0..7] 22
PCIE_CTX_GRX_N[0..7] 22
PCIE_CTX_GRX_P[0..7] 22
+1.05VS
+1.05VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(1/7) DMI,FDI,PEG
Custom
4 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(1/7) DMI,FDI,PEG
Custom
4 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(1/7) DMI,FDI,PEG
Custom
4 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
C1 0.22U_0402_10V6KDIS@C1 0.22U_0402_10V6KDIS@
1 2
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-2_IVY BRIDGE
ME@
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-2_IVY BRIDGE
ME@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI
J22
PEG_ICOMPO
J21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J35
PEG_RX#[4]
J32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG_RX#[10]
E34
PEG_RX#[11]
E32
PEG_RX#[12]
D33
PEG_RX#[13]
D31
PEG_RX#[14]
B33
PEG_RX#[15]
C32
PEG_RX[0]
J33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J30
PEG_TX#[8]
J28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J29
PEG_TX[8]
J27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD#
B16
eDP_ICOMPO
A17
C23 0.22U_0402_10V6KDIS@C23 0.22U_0402_10V6KDIS@
1 2
C3 0.22U_0402_10V6KDIS@C3 0.22U_0402_10V6KDIS@
1 2
C18 0.22U_0402_10V6KDIS@C18 0.22U_0402_10V6KDIS@
1 2
C5 0.22U_0402_10V6KDIS@C5 0.22U_0402_10V6KDIS@
1 2
R2 24.9_0402_1%R2 24.9_0402_1%
1 2
C20 0.22U_0402_10V6KDIS@C20 0.22U_0402_10V6KDIS@
1 2
C7 0.22U_0402_10V6KDIS@C7 0.22U_0402_10V6KDIS@
1 2
C22 0.22U_0402_10V6KDIS@C22 0.22U_0402_10V6KDIS@
1 2
C2 0.22U_0402_10V6KDIS@C2 0.22U_0402_10V6KDIS@
1 2
C24 0.22U_0402_10V6KDIS@C24 0.22U_0402_10V6KDIS@
1 2
C17 0.22U_0402_10V6KDIS@C17 0.22U_0402_10V6KDIS@
1 2
C4 0.22U_0402_10V6KDIS@C4 0.22U_0402_10V6KDIS@
1 2
C19 0.22U_0402_10V6KDIS@C19 0.22U_0402_10V6KDIS@
1 2
R3 10K_0402_5%@R3 10K_0402_5%@
1 2
C6 0.22U_0402_10V6KDIS@C6 0.22U_0402_10V6KDIS@
1 2
C21 0.22U_0402_10V6KDIS@C21 0.22U_0402_10V6KDIS@
1 2
C8 0.22U_0402_10V6KDIS@C8 0.22U_0402_10V6KDIS@
1 2
R1 24.9_0402_1%R1 24.9_0402_1%
1 2
1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
Buffered reset to CPU
For 26 Pin XDP Conn.
DDR3 Compensation Signals
PU/PD for JTAG signals
Processor Pullups
P+
P+
P+
P+
P+
P+
P+
PM_SYS_PWRGD_BUF
BUFO_CPU_RST# BUF_CPU_RST#
PLT_RST#
H_PECI
H_CATERR#
H_THRMTRIP#
H_PROCHOT#_R
H_PM_SYNC
H_CPUPWRGD_R
PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF
BUF_CPU_RST#
XDP_BPM#1
XDP_BPM#0
XDP_BPM#6
XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#7
XDP_TRST#
XDP_TMS
XDP_TCK
XDP_PREQ#
XDP_PRDY#
XDP_TDO
XDP_TDI
SM_RCOMP0
SM_RCOMP2
SM_RCOMP1
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
XDP_DBRESET#_C
H_PROCHOT#H_PROCHOT#
PM_DRAM_PWRGD PM_SYS_PWRGD_BUF
PCH_PLTRST#17
PM_DRAM_PWRGD15
RUN_ON_CPU1.5VS3#9
H_CPUPWRGD18,5
PBTN_OUT#15,41
XDP_CFG07
SYS_PWROK15
CLK_XDP_CLK14
CLK_XDP_CLK#14
PLT_RST#14,17,22,38,39,40,41,42
H_SNB_IVB#18
H_PECI18,41
H_PROCHOT#41
H_THRMTRIP#18
H_PM_SYNC15
H_CPUPWRGD18,5
CLK_CPU_DMI 14
CLK_CPU_DMI# 14
H_DRAMRST# 6
XDP_DBRESET# 15
+3VS +1.05VS+1.5V_CPU_VDDQ+3VALW+3VS
+3VS
+1.05VS
+1.05VS
+1.05VS
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(2/7) PM,XDP,CLK
Custom
5 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(2/7) PM,XDP,CLK
Custom
5 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
Size Document Number Rev
Date: Sheet of
Security Classification
LC Future Center Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Issued Date
Deciphered Date
Title
NM-A041
NM-A041NM-A041
NM-A041
1.A
PROCESSOR(2/7) PM,XDP,CLK
Custom
5 59
Thursday, November 01, 2012
2012/07/01
2014/07/01
C74
0.1U_0402_16V4Z
C74
0.1U_0402_16V4Z
1
2
R240 0_0402_5%R240 0_0402_5%
1 2
R312 200_0402_1%R312 200_0402_1%
1 2
R242
43_0402_1%
R242
43_0402_1%
1 2
R320
75_0402_5%
R320
75_0402_5%
12
R279 0_0402_5%@R279 0_0402_5%@
1 2
R44
0_0402_5%
@
R44
0_0402_5%
@
12
G
D
S
Q13
2N7002K_SOT23-3
@
G
D
S
Q13
2N7002K_SOT23-3
@
2
13
R281 62_0402_5%R281 62_0402_5%
1 2
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-2_IVY BRIDGE
ME@
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-2_IVY BRIDGE
ME@
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPW ROK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R191 1K_0402_1%@R191 1K_0402_1%@
1 2
R295
10K_0402_5%
R295
10K_0402_5%
1 2
R321 1K_0402_5%R321 1K_0402_5%
1 2
R326 51_0402_5%R326 51_0402_5%
1 2
R194 0_0402_5%@R194 0_0402_5%@
1 2
R322 130_0402_5%R322 130_0402_5%
1 2
C73
0.1U_0402_16V4Z
C73
0.1U_0402_16V4Z
1
2
R327 1K_0402_5%R327 1K_0402_5%
1 2
R20 140_0402_1%R20 140_0402_1%
1 2
R323 51_0402_5%R323 51_0402_5%
1 2
R296 51_0402_5%R296 51_0402_5%
1 2
R267 0_0402_5%R267 0_0402_5%
1 2
R331
200_0402_5%
R331
200_0402_5%
12
R224 1K_0402_1%@R224 1K_0402_1%@
1 2
R324 10K_0402_5%R324 10K_0402_5%
1 2
R297 1K_0402_5%R297 1K_0402_5%
1 2
R333 0_0402_5%
@
R333 0_0402_5%
@
1 2
R325 0_0402_5%@R325 0_0402_5%@
1 2
R298 56_0402_5%R298 56_0402_5%
1 2
R236 25.5_.402_1%R236 25.5_.402_1%
1 2
U12
74AHC1G09GW_TSSOP5
U12
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O
4
P
5
R299 51_0402_5%R299 51_0402_5%
1 2
R237 1K_0402_1%@R237 1K_0402_1%@
1 2
C75 220P_0402_50V7K@C75 220P_0402_50V7K@
1 2
R354 0_0402_5%R354 0_0402_5%
1 2
R301 0_0402_5%@R301 0_0402_5%@
1 2
R238 51_0402_5%R238 51_0402_5%
1 2
U7
SN74LVC1G07DCKR_SC70-5
U7
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y
4
P
5
R355 0_0402_5%R355 0_0402_5%
1 2
R306 10K_0402_5%@R306 10K_0402_5%@
1 2
R239
39_0402_5%
@
R239
39_0402_5%
@
12
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