Verilog设计数字系统入门指南

verilog

数字设计

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《数字系统设计使用Verilog》是一本由Charles H. Roth Jr., Lizy Kurian John, 和 ByeongKil Lee合著的优秀教材，专为学习和理解数字系统设计中的Verilog编程语言而编撰。该书针对初学者和进阶工程师，旨在通过深入浅出的方式介绍逻辑设计基础知识，并将这些理论与实际应用中的Verilog编程相结合。本书的第一章回顾了逻辑设计的基本概念，包括： 1. **组合逻辑**：这部分介绍了基本的逻辑门结构和逻辑函数，帮助读者理解电路如何根据输入信号实时计算输出。 2. **布尔代数与代数简化**：作者详细解释了布尔运算规则，以及如何利用代数方法简化复杂的逻辑表达式，以提高电路效率和设计简洁性。 3. **卡诺图（Karnaugh Maps）**：卡诺图是一种可视化工具，用于查找最小项表达式和进行逻辑优化，这对于理解和设计高效电路至关重要。 4. **使用NAND和NOR门的设计**：作者引导读者通过这两种基础门来构建更复杂的逻辑电路，从而掌握基本设计原则。 5. **组合电路中的冲突（Hazards）**：探讨了在时序逻辑中可能出现的同步和异步冒险现象，这对于理解和避免潜在问题非常重要。 6. **触发器与寄存器（Flip-Flops and Latches）**：这一部分深入解释了时序逻辑元件，如D型、JK型和T型触发器，以及它们在存储和传递状态中的作用。 7. **梅耶（Mealy）序列电路设计**：介绍了基于事件驱动的序列电路设计，强调了输入和输出之间的时序关系。 8. **摩尔（Moore）序列电路设计**：讲解了另一种常用的序列电路设计范式，其中输出只依赖于当前状态，而不考虑输入。 9. **等效状态和状态表简化**：探讨了如何分析和简化状态机，以减少设计复杂性和实现精简。 10. **Verilog编程基础**：在理论讲解之后，作者逐步引入Verilog语言，让读者能在实践中应用所学的逻辑设计原理。整本书通过理论教学和实例演示，为读者提供了一个系统的学习框架，不仅适用于理论学习，也是数字系统设计师必备的实用参考书。对于想要进一步探索数字系统设计和Verilog编程的人来说，这是一本不可多得的指南。

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6 Chapter 1 Review of Logic Design Fundamentals

should be chosen so that they will combine with or eliminate other terms. For

example,

WX 1 XY 1 X9Z9 1 WY9Z9 (Add WZ9 by the consensus theorem.)

5 WX 1 XY 1 X9Z9 1 WY9Z9 1 WZ9 (eliminate WY9Z9)

5 WX 1 XY 1 X9Z9 1 WZ9 (eliminate WZ9)

5 WX 1 XY 1 X9Z9

When multiplying out or factoring an expression, in addition to using

the ordinary distributive law (1‑12), the second distributive law (1‑12D)

and theorem (1‑20) are particularly useful. The following is an exam‑

ple of multiplying out to convert from a product of sums to a sum of

products:

(A 1 B 1 D)(A 1 B9 1 C9)(A9 1 B 1 D9)(A9 1 B 1 C9)

5 (A 1 (B 1 D)(B9 1 C9))(A9 1 B 1 C9D9) (by (1‑12D))

5 (A 1 BC9 1 B9D)(A9 1 B 1 C9D9) (by (1‑20))

5 A(B 1 C9D9) 1 A9(BC9 1 B9D) (by (1‑20))

5 AB 1 AC9D9 1 A9BC9 1 A9B9D (by (1‑12))

Note that the second distributive law (1‑12D) and theorem (1‑20) were

applied before the ordinary distributive law. Any Boolean expression can

be factored by using the two distributive laws (1‑12 and 1‑12D) and theorem

(1‑20). As an example of factoring, read the steps in the preceding example

in the reverse order.

The following theorems apply to exclusive‑OR:

X ! 0 5 X (1‑23)

X ! 1 5 X9 (1‑24)

X ! X 5 0 (1‑25)

X ! X9 5 1 (1‑26)

X ! Y 5 Y ! X (commutative law) (1‑27)

(X ! Y) ! Z 5 X ! (Y ! Z) 5 X ! Y ! Z (associative law) (1‑28)

X(Y ! Z) 5 XY ! XZ (distributive law) (1‑29)

(X ! Y)9 5 X ! Y9 5 X9 ! Y 5 XY 1 X9Y9 (1‑30)

The expression for Sum (equation (1‑2)) can be rewritten in terms of exclusive‑OR

by using (1‑1) and (1‑30):

Sum 5 X9(Y9C

1 YC

9) 1 X(Y9C

9 1 YC

)

5 X9(Y ! C

) 1 X(Y ! C

)9 5 X ! Y ! C

(1‑31)

The simplication rules that you studied in this section are important when a

circuit has to be optimized to use a lower number of gates. The existence of equiv‑

alent forms also helps when mapping circuits into particular target devices where

only certain types of logic (e.g., NAND only or NOR only ) are available.

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1.3 Karnaugh Maps 7

1.3 Karnaugh Maps

Karnaugh maps (K‑maps) provide a convenient way to simplify logic functions

of three to ve variables. Figure 1‑3 shows a four‑variable Karnaugh map. Each

square in the map represents one of the 16 possible minterms of four variables. A 1

in a square indicates that the minterm is present in the function, and a 0 (or blank)

indicates that the minterm is absent. An X in a square indicates that we don’t care

whether the minterm is present or not. Don’t cares arise under two conditions:

(1) The input combination corresponding to the don’t care can never occur, and

(2) the input combination can occur, but the circuit output is not specied for this

input condition.

The variable values along the edge of the map are ordered so that adjacent

squares on the map differ in only one variable. The rst and last columns and the

top and bottom rows of the map are considered to be adjacent. Two 1s in adjacent

squares can be combined by eliminating one variable using xy 1 xy9 5 x. Figure 1‑3

shows a four‑variable function with nine minterms and two don’t cares. Minterms

A9BC9D and A9BCD differ only in the variable C, so they can be combined to form

A9BD, as indicated by a loop on the map. Four 1s in a symmetrical pattern can be

combined to eliminate two variables. The 1s in the four corners of the map can be

combined as follows:

(A9B9C9D9 1 AB9C9D9) 1 (A9B9CD9 1 AB9CD9) 5 B9C9D9 1 B9CD9 5 B9D9

as indicated by the loop. Similarly, the six 1s and two Xs in the bottom half of the

map combine to eliminate three variables and form the term C. The resulting sim‑

plied function is

F 5 A9BD 1 B9D9 1 C

0100 11 10

Four corner terms

combine to give B9D9

A9BD

F = S m (0, 2, 3, 5, 6, 7, 8, 10, 11) + S d (14, 15)

= C + B9D9 + A9BD

000

(a) Location of minterms (b) Loopin

terms

513

14 10

0100 11 10

FIGURE 1-3: Four-

Variable Karnaugh Maps

The minimum sum‑of‑products representation of a function consists of a sum

of prime implicants. A group of one, two, four, or eight adjacent 1s on a map rep‑

resents a prime implicant if it cannot be combined with another group of 1s to elim‑

inate a variable. A prime implicant is essential if it contains a 1 that is not contained

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8 Chapter 1 Review of Logic Design Fundamentals

in any other prime implicant. When nding a minimum sum of products from a

map, essential prime implicants should be looped rst, and then a minimum number

of prime implicants to cover the remaining 1s should be looped. The Karnaugh map

shown in Figure 1‑4 has ve prime implicants and three essential prime implicants.

A9C9 is essential because minterm m

is not covered by any other prime implicant.

Similarly, ACD is essential because of m

, and A9B9D9 is essential because of

. After the essential prime implicants have been looped, all 1s are covered except

. Since m

can be covered by either prime implicant A9BD or BCD, F has two

minimum forms:

F 5 A9C9 1 A9B9D9 1 ACD 1 A9BD

and F 5 A9C9 1 A9B9D9 1 ACD 1 BCD

FIGURE 1-4: Selection of

Prime Implicants

0100 11 10

A9C9

ACD

A9B9D9

2614 10

15 11

412

513

When don’t cares (Xs) are present on the map, the don’t cares are treated like

1s when forming prime implicants, but the Xs are ignored when nding a minimum

set of prime implicants to cover all the 1s. The following procedure can be used to

obtain a minimum sum of products from a Karnaugh map:

1. Choose a minterm (a 1) that has not yet been covered.

2. Find all 1s and Xs adjacent to that minterm. (Check the n adjacent squares

on an n‑variable map.)

3. If a single term covers the minterm and all the adjacent 1s and Xs, then that

term is an essential prime implicant, so select that term. (Note that don’t

cares are treated as 1s in steps 2 and 3 but not in step 1.)

4. Repeat steps 1, 2, and 3 until all essential prime implicants have been chosen.

5. Find a minimum set of prime implicants that cover the remaining 1s on the

map. (If there is more than one such set, choose a set with a minimum num‑

ber of literals.)

To nd a minimum product of sums from a Karnaugh map, loop the 0s instead

of the 1s. Since the 0s of F are the 1s of F9, looping the 0s in the proper way gives

the minimum sum of products for F9, and the complement is the minimum product

of sums for F. For Figure 1‑3, we can rst loop the essential prime implicants of

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10 Chapter 1 Review of Logic Design Fundamentals

Next we will discuss a general method of simplifying functions using map‑

entered variables. In general, if a variable P

is placed in square m

of a map of

function F, this means that F 5 1 when P

5 1 and the variables are chosen so that

j

51. Given a map with variables P

, P

, . . . entered into some of the squares,

the minimum sum‑of‑products form of F can be found as follows: Find a sum‑

of‑products expression for F of the form

F 5 MS

1 P

1 ? ? ? (1‑32)

where



is the minimum sum obtained by setting P

5 P

5 ? ? ? 5 0.



is the minimum sum obtained by setting P

5 1, P

5 0 ( j Þ 1), and replacing

all 1s on the map with don’t cares.



is the minimum sum obtained by setting P

5 1, P

5 0 ( j Þ 2), and replacing

all 1s on the map with don’t cares.

Corresponding minimum sums can be found in a similar way for any remaining

map‑entered variables.

The resulting expression for F will always be a correct representation of F. This

expression will be a minimum sum provided that the values of the map‑entered

variables can be assigned independently. On the other hand, the expression will not

generally be a minimum sum if the variables are not independent (for example, if

5 P

9).

For the example of Figure 1‑5, maps for finding MS

, MS

, and MS

are

shown where E corresponds to P

and F corresponds to P

. Note that it is not

required to draw a map for E51, F51, because E51 already covers cases with

E51, F50 and E51, F51. The resulting expression is a minimum sum of prod‑

ucts for G:

G 5 A9B9 1 ACD 1 EA9D 1 FAD

After some practice, it should be possible to write the minimum expression

directly from the original map without rst plotting individual maps for each of the

minimum sums.

FIGURE 1-5: Simpliﬁcation

Using Map-Entered

Variables

0100 11 10

0100

E = F = 0

= A9B9 + ACD

E = 1, F = 0

= A9D

E = 0, F = 1

= AD

11 10

0100 11 10

E X

0100 11 10

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