Contents
Preface vii
Chapter 1 Review of Logic Design Fundamentals 1
1.1 Combinational Logic 1
1.2
Boolean Algebra and Algebraic Simplication
3
1.3
Karnaugh
Maps 7
1.4
Designing with NAND and NOR Gates
11
1.5
Hazards in Combinational Circuits
13
1.6
Flip-Flops and Latches
15
1.7
Mealy Sequential Circuit Design
17
1.8
Design of a Moore Sequential Circuit
25
1.9
Equivalent States and Reduction of State Tables
28
1.10
Sequential Circuit Timing 30
1.11
Tristate Logic and Busses
47
Problems
48
Chapter 2 Introduction to Verilog
®
58
2.1 Computer-Aided Design 59
2.2
Hardware Description Languages
62
2.3
Verilog Description of Combinational Circuits
64
2.4
Verilog
Modules 68
2.5
Verilog
Assignments 73
2.6
Procedural
Assignments 74
2.7
Modeling Flip-Flops Using Always Block
78
2.8
Always Blocks Using Event Control Statements
82
2.9
Delays in Verilog
84
2.10
Compilation, Simulation, and Synthesis of Verilog Code 87
2.11
Verilog Data Types and Operators
93
2.12
Simple Synthesis Examples
98
2.13
Verilog Models for Multiplexers
102
2.14
Modeling Registers and Counters Using Verilog Always Statements
104
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