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Contents
1. Generic Serial Flash Interface Intel
®
FPGA IP Core User Guide.......................................3
1.1. Device Family Support............................................................................................4
1.2. Signals.................................................................................................................4
1.3. Parameters........................................................................................................... 6
1.4. Register Map.........................................................................................................6
1.5. Using Generic Serial Flash Interface IP..................................................................... 9
1.5.1. Control Status Register Operations...............................................................9
1.5.2. Memory Operations..................................................................................10
1.6. Generic Serial Flash Interface Intel FPGA IP Core Reference Design............................ 11
1.6.1. Hardware and Software Requirements........................................................ 11
1.6.2. Functional Description.............................................................................. 12
1.6.3. Creating Nios II Hardware System..............................................................14
1.6.4. Integrating Modules into Intel Quartus Prime Project.................................... 16
1.6.5. Programming the .sof File......................................................................... 16
1.6.6. Building Application Software System using Nios II Software Build Tools.......... 17
1.7. Flash Access Using the Generic Serial Flash Interface Intel FPGA IP Core..................... 19
1.7.1. Flash Operations that Require Operation Code............................................. 19
1.7.2. Flash Operations to Read Flash Registers.....................................................20
1.7.3. Flash Operations to Write Flash Registers.................................................... 21
1.7.4. Flash Operations that Require An Address................................................... 22
1.7.5. Read Memory from the Flash..................................................................... 23
1.7.6. Program Flash......................................................................................... 25
1.8. Generic Serial Flash Interface Intel FPGA IP Core User Guide Archives.........................26
1.9. Document Revision History for the Generic Serial Flash Interface Intel FPGA IP
Core User Guide................................................................................................27
Contents
Generic Serial Flash Interface Intel FPGA IP Core User Guide
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1. Generic Serial Flash Interface Intel
®
FPGA IP Core User
Guide
The Generic Serial Flash Interface Intel
®
FPGA IP core provides access to Serial
Peripheral Interface (SPI) flash devices. The Generic Serial Flash Interface IP is a
more efficient alternative compared to the ASMI Parallel and ASMI Parallel II Intel
FPGA IP cores. The Generic Serial Flash Interface Intel FPGA IP core supports Intel
configuration devices as well as flash from different vendors. Intel recommends you to
use the Generic Serial Flash Interface Intel FPGA IP core for new designs.
You can use the Generic Serial Flash Interface IP to write the following data to the
flash device:
• Configuration memory
(1)
—configuration data for Active Serial (AS) configuration
scheme
• General purpose memory— application-specific data
The Generic Serial Flash Interface IP supports the following features:
• Single, dual or quad I/O mode
• Direct flash access via the Avalon Memory Mapped (Avalon-MM) slave interface
which allows the controller to directly execute codes from the flash
• Up to 3 multiple flash device support (Intel Arria
®
10 and Intel Cyclone
®
10 GX
devices only)
• Generic control register for accessing flash control status registers
• Programmable clock generator with run-time baud rate change for device clock
• Programmable chip select delay
• Read data capturing logic when running with high frequency
• FPGA active serial memory interface (ASMI) block atom connection to the active
serial (AS) pins or export to FPGA I/O pins
Related Information
• Generic Serial Flash Interface Intel FPGA IP Core Reference Design on page 11
• Generic Serial Flash Interface Intel FPGA IP Core Reference Design Files
• How do I enable Micron's MT25Q device support in replacement to End Of Life
(EOL) EPCQ(>=256Mb) and EPCQ-L devices?
• Configuration Devices
Provides more information on the third-party flash support.
• Using the Generic Serial Flash Interface (ODEVGSFI) Training Course
(1)
The supported flash devices for configuration memory are, EPCQ, EPCQ-A, EPCQ-L, and
Micron* MT25Q (256Mb to 2Gb) devices.
UG-20161 | 2018.11.09
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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

1.1. Device Family Support
The Generic Serial Flash Interface IP is supported in the following devices:
• Intel Arria 10
• Intel Cyclone 10 GX
• Intel Cyclone 10 LP
• Intel MAX
®
10 (For general purpose memory only)
• Stratix
®
V
• Arria V
• Cyclone V
• Stratix IV
• Cyclone IV
• Arria II
Related Information
Configuration Devices
Provides more information about the third-party flash support.
1.2. Signals
Figure 1. Signal Block Diagram
Generic Serial Flash
Interface Intel FPGA IP
reset
clk
avl_csr_read
flash_ncs
avl_csr_wrdata
avl_mem_write
avl_mem_burstcount
avl_mem_waitrequest
avl_mem_readdata
avl_mem_rddata_valid
avl_mem_read
avl_mem_addr
avl_mem_wrdata
avl_mem_byteenble flash_dclk
flash_data
avl_csr_write
avl_csr_addr avl_csr_rddata
avl_csr_rddata_valid
avl_csr_waitrequest
1. Generic Serial Flash Interface Intel
®
FPGA IP Core User Guide
UG-20161 | 2018.11.09
Generic Serial Flash Interface Intel FPGA IP Core User Guide
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Table 1. Ports Description
Signal Width Direction Description
Avalon
®
-MM slave interface for CSR (avl_csr)
avl_csr_addr
6 Input Avalon-MM address bus. The address bus is in word addressing.
avl_csr_read
1 Input Avalon-MM read control to the CSR.
avl_csr_rddata
32 Output Avalon-MM read data bus from the CSR.
avl_csr_write
1 Input Avalon-MM write control to the CSR.
avl_csr_wrdata
32 Input Avalon-MM write data bus to CSR.
avl_csr_waitrequest
1 Output Avalon-MM waitrequest control from the CSR
avl_csr_rddata_valid
1 Output Avalon-MM read data valid that indicates the CSR read data is
available.
Avalon-MM slave interface for memory access (avl_ mem)
avl_mem_write
1 Input Avalon-MM write control to the memory
avl_mem_burstcount
7 Input Avalon-MM burst count for the memory. The value range from 1 to
64 (Max page size).
avl_mem_waitrequest
1 Output Avalon-MM waitrequest control from the memory.
avl_mem_read
1 Input Avalon-MM read control to the memory
avl_mem_addr
N Input Avalon-MM address bus. The address bus is in word addressing.
The width of the address depends on the flash memory density.
If you are using Intel Arria 10, and Intel Cyclone 10 GX or any
supported devices with general purpose I/O with multiples flashes,
write the CSR to select the chip select. The IP targets the selected
flash when being accessed via this address.
avl_mem_wrdata
32 Input Avalon-MM write data bus to the memory
avl_mem_readddata
32 Output Avalon-MM read data bus from the memory.
avl_mem_rddata_valid
1 Output Avalon-MM read data valid that indicates the memory read data is
available.
avl_mem_byteenble
4 Input Avalon-MM write data enable bus to memory. During bursting
mode, byteenable bus will be logic high, 4’b1111.
Clock and Reset
clk
1 Input Input clock to clock the IP core.
reset
1 Input Asynchronous reset to reset the IP core.
Interrupt
Irq
1 Output Interrupt signal that indicate if there is an illegal write or illegal
erase.
Conduit Interface
(2)
flash_data
4 Bidirectional Input or output port to feed data from the flash device.
flash_dclk
1 Output
Provides clock signal to the flash device.
flash_ncs
1/3 Output
Provides the ncs signal to the flash device.
(2)
Available when you enable the Enable SPI pins interface parameter.
1. Generic Serial Flash Interface Intel
®
FPGA IP Core User Guide
UG-20161 | 2018.11.09
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Generic Serial Flash Interface Intel FPGA IP Core User Guide
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