《计算机组成与设计》5th版：硬件/软件接口英文原版

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"《计算机组成与设计硬件/软件接口原书第5版》英文版PDF，高清晰度，包含书签" 《计算机组成与设计》(Computer Organization and Design)是计算机科学领域的一本经典教材，由David A. Patterson和John L. Hennessy合著，现在已经更新到了第五版。这本书深入浅出地探讨了计算机硬件与软件之间的接口，即计算机组织与设计的基本原理。在计算机科学教育中，选择合适的教材往往需要在教学方法、内容覆盖、表述质量、严谨程度以及成本等多个方面做出权衡。而《计算机组成与设计》正是这样一本在所有方面都表现出色的教科书，它不仅是最顶尖的计算机组织教材，也树立了其他计算机科学教材应该追求的标准。第五版的更新反映了计算机领域的最新进展。随着从桌面计算向移动计算的转变，再到大数据和云计算的兴起，书中增加了对嵌入式处理器（如ARM架构）的深入讨论，这些处理器在现代设备中扮演着关键角色。同时，新版还介绍了如何通过硬件和软件的交互来提升性能，这是现代高性能计算的关键。此外，云 computing 的概念也被纳入其中，使读者能够理解大规模分布式系统的运作机制。对于新一代的计算机科学学习者——千禧一代，这本书不仅是计算机体系结构的基础读物，更是理解当今数字世界核心技术不可或缺的资源。无论是对计算机硬件感兴趣的工程师，还是希望深入了解软件如何在不同硬件平台上运行的程序员，这本书都能提供宝贵的洞见。书中的案例研究、问题集和练习有助于读者巩固理论知识，并将理论应用于实践。《计算机组成与设计》第五版是一本全面、权威的教材，不仅涵盖了计算机系统的基础知识，还紧跟技术发展的步伐，不断更新内容，确保读者能够掌握最新的硬件和软件设计理念。无论你是初学者还是经验丰富的专业人士，这本书都将为你打开一扇通往计算机硬件世界的门，帮助你理解计算机硬件与软件是如何协同工作的。

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Preface

 e most beautiful thing we can experience is the mysterious. It is the

source of all true art and science.

Albert Einstein, What I Believe, 1930

About This Book

We b e l i e v e t h a t l e a r n i n g i n c o m p u t e r s c i e n c e a n d e n g i n e e r i n g s h o u l d r e  ect

the current state of the  eld, as well as introduce the principles that are shaping

computing. We also feel that readers in every specialty of computing need

to appreciate the organizational paradigms that determine the capabilities,

performance, energy, and, ultimately, the success of computer systems.

M o d e r n c o m p u t e r t e c h n o l o g y r e q u i r e s p r o f e s s i o n a l s o f e v e r y c o m p u t i n g

specialty to understand both hardware and so ware.  e interaction between

hardware and so ware at a variety of levels also o ers a framework for understanding

the fundamentals of computing. Whether your primary interest is hardware or

so ware, computer science or electrical engineering, the central ideas in computer

organization and design are the same.  us, our emphasis in this book is to show

the relationship between hardware and so ware and to focus on the concepts that

are the basis for current computers.

 e recent switch from uniprocessor to multicore microprocessors con rmed

the soundness of this perspective, given since the  rst edition. While programmers

could ignore the advice and rely on computer architects, compiler writers, and silicon

engineers to make their programs run faster or be more energy-e cient without

change, that era is over. For programs to run faster, they must become parallel.

While the goal of many researchers is to make it possible for programmers to be

unaware of the underlying parallel nature of the hardware they are programming,

it will take many years to realize this vision. Our view is that for at least the next

decade, most programmers are going to have to understand the hardware/so ware

interface if they want programs to run e ciently on parallel computers.

 e audience for this book includes those with little experience in assembly

language or logic design who need to understand basic computer organization as

well as readers with backgrounds in assembly language and/or logic design who

want to learn how to design a computer or understand how a system works and

why it performs as it does.

xvi Preface

About the Other Book

S o m e r e a d e r s m a y b e f a m i l i a r w i t h Computer Architecture: A Quantitative

Approach , p o p u l a r l y k n o w n a s H e n n e s s y a n d P a t t e r s o n . (  is book in turn is

o en called Patterson and Hennessy.) Our motivation in writing the earlier book

was to describe the principles of computer architecture using solid engineering

fundamentals and quantitative cost/performance tradeo s. We used an approach

that combined examples and measurements, based on commercial systems, to

create realistic design experiences. Our goal was to demonstrate that computer

architecture could be learned using quantitative methodologies instead of a

descriptive approach. It was intended for the serious computing professional who

wanted a detailed understanding of computers.

A m a j o r i t y o f t h e r e a d e r s f o r t h i s b o o k d o n o t p l a n t o b e c o m e c o m p u t e r

architects.  e performance and energy e ciency of future so ware systems will

be dramatically a ected, however, by how well so ware designers understand the

basic hardware techniques at work in a system.  us, compiler writers, operating

system designers, database programmers, and most other so ware engineers need

a  rm grounding in the principles presented in this book. Similarly, hardware

designers must understand clearly the e ects of their work on so ware applications.

 us, we knew that this book had to be much more than a subset of the material

in Computer Architecture , a n d t h e m a t e r i a l w a s e x t e n s i v e l y r e v i s e d t o m a t c h t h e

di erent audience. We were so happy with the result that the subsequent editions of

Computer Architecture w e r e r e v i s e d t o r e m o v e m o s t o f t h e i n t r o d u c t o r y m a t e r i a l ;

hence, there is much less overlap today than with the  rst editions of both books.

Changes for the Fifth Edition

We h a d s i x m a j o r g o a l s f o r t h e   h edition of Computer Organization and Design:

demonstrate the importance of understanding hardware with a running example;

highlight major themes across the topics using margin icons that are introduced

early; update examples to re ect changeover from PC era to PostPC era; spread the

material on I/O throughout the book rather than isolating it into a single chapter;

update the technical content to re ect changes in the industry since the publication

of the fourth edition in 2009; and put appendices and optional sections online

instead of including a CD to lower costs and to make this edition viable as an

electronic book.

B e f o r e d i s c u s s i n g t h e g o a l s i n d e t a i l , l e t ’s l o o k a t t h e t a b l e o n t h e n e x t p a g e . I t

shows the hardware and so ware paths through the material. Chapters1, 4, 5, and

6 are found on both paths, no matter what the experience or the focus. Chapter1

discusses the importance of energy and how it motivates the switch from single

core to multicore microprocessors and introduces the eight great ideas in computer

architecture. Chapter2 is likely to be review material for the hardware-oriented,

but it is essential reading for the so ware-oriented, especially for those readers

interested in learning more about compilers and object-oriented programming

languages. Chapter 3 is for readers interested in constructing a datapath or in

xviii Preface

learning more about  oating-point arithmetic. Some will skip parts of Chapter3,

either because they don’t need them or because they o er a review. However, we

introduce the running example of matrix multiply in this chapter, showing how

subword parallels o ers a fourfold improvement, so don’t skip sections 3.6 to 3.8.

Chapter4 explains pipelined processors. Sections 4.1, 4.5, and 4.10 give overviews

and Section 4.12 gives the next performance boost for matrix multiply for those with

a so ware focus.  ose with a hardware focus, however, will  nd that this chapter

presents core material; they may also, depending on their background, want to read

Appendix C on logic design  rst.  e last chapter on multicores, multiprocessors,

and clusters, is mostly new content and should be read by everyone. It was

signi cantly reorganized in this edition to make the  ow of ideas more natural

and to include much more depth on GPUs, warehouse scale computers, and the

hardware-so ware interface of network interface cards that are key to clusters.

 e  rst of the six goals for this  rth edition was to demonstrate the importance

of understanding modern hardware to get good performance and energy e ciency

with a concrete example. As mentioned above, we start with subword parallelism

in Chapter3 to improve matrix multiply by a factor of 4. We double performance

in Chapter4 by unrolling the loop to demonstrate the value of instruction level

parallelism. Chapter5 doubles performance again by optimizing for caches using

blocking. Finally, Chapter6 demonstrates a speedup of 14 from 16 processors by

using thread-level parallelism. All four optimizations in total add just 24 lines of C

code to our initial matrix multiply example.

 e second goal was to help readers separate the forest from the trees by

identifying eight great ideas of computer architecture early and then pointing out

all the places they occur throughout the rest of the book. We use (hopefully) easy

to remember margin icons and highlight the corresponding word in the text to

remind readers of these eight themes.  ere are nearly 100 citations in the book.

No chapter has less than seven examples of great ideas, and no idea is cited less than

 ve times. Performance via parallelism, pipelining, and prediction are the three

most popular great ideas, followed closely by Moore’s Law.  e processor chapter

(4) is the one with the most examples, which is not a surprise since it probably

received the most attention from computer architects.  e one great idea found in

every chapter is performance via parallelism, which is a pleasant observation given

the recent emphasis in parallelism in the  eld and in editions of this book.

 e third goal was to recognize the generation change in computing from the

PC era to the PostPC era by this edition with our examples and material.  us,

Chapter1 dives into the guts of a tablet computer rather than a PC, and Chapter6

describes the computing infrastructure of the cloud. We also feature the ARM,

which is the instruction set of choice in the personal mobile devices of the PostPC

era, as well as the x86 instruction set that dominated the PC Era and (so far)

dominates cloud computing.

 e fourth goal was to spread the I/O material throughout the book rather

than have it in its own chapter, much as we spread parallelism throughout all the

chapters in the fourth edition. Hence, I/O material in this edition can be found in

Preface xix

Sections 1.4, 4.9, 5.2, 5.5, 5.11, and 6.9.  e thought is that readers (and instructors)

are more likely to cover I/O if it’s not segregated to its own chapter.

 is is a fast-moving  eld, and, as is always the case for our new editions, an

important goal is to update the technical content.  e running example is the ARM

Cortex A8 and the Intel Core i7, re ecting our PostPC Era. Other highlights include

an overview the new 64-bit instruction set of ARMv8, a tutorial on GPUs that

explains their unique terminology, more depth on the warehouse scale computers

that make up the cloud, and a deep dive into 10 Gigabyte Ethernet cards.

To keep the main book short and compatible with electronic books, we placed

the optional material as online appendices instead of on a companion CD as in

prior editions.

Finally, we updated all the exercises in the book.

W h i l e s o m e e l e m e n t s c h a n g e d , w e h a v e p r e s e r v e d u s e f u l b o o k e l e m e n t s f r o m

prior editions. To make the book work better as a reference, we still place de nitions

of new terms in the margins at their  rst occurrence.  e book element called

“Understanding Program Performance” sections helps readers understand the

performance of their programs and how to improve it, just as the “Hardware/So ware

Interface” book element helped readers understand the tradeo s at this interface.

“ e Big Picture” section remains so that the reader sees the forest despite all the

trees. “Check Yourself” sections help readers to con rm their comprehension of the

material on the  rst time through with answers provided at the end of each chapter.

 is edition still includes the green MIPS reference card, which was inspired by the

“Green Card” of the IBM System/360.  is card has been updated and should be a

handy reference when writing MIPS assembly language programs.

Changes for the Fifth Edition

We h a v e c o l l e c t e d a g r e a t d e a l o f m a t e r i a l t o h e l p i n s t r u c t o r s t e a c h c o u r s e s u s i n g

this book. Solutions to exercises,  gures from the book, lecture slides, and other

materials are available to adopters from the publisher. Check the publisher’s Web

site for more information:

textbooks.elsevier.com/9780124077263

Concluding Remarks

I f y o u r e a d t h e f o l l o w i n g a c k n o w l e d g m e n t s s e c t i o n , y o u w i l l s e e t h a t w e w e n t t o

great lengths to correct mistakes. Since a book goes through many printings, we

have the opportunity to make even more corrections. If you uncover any remaining,

resilient bugs, please contact the publisher by electronic mail at cod5bugs@mkp.

com or by low-tech mail using the address found on the copyright page.

 is edition is the second break in the long-standing collaboration between

Hennessy and Patterson, which started in 1989.  e demands of running one of

the world’s great universities meant that President Hennessy could no longer make

the substantial commitment to create a new edition.  e remaining author felt

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