英特尔 Stratix 10 高性能设计白皮书

Intel

®

Stratix

®

10 High-Performance

Design Handbook

Updated for Intel

®

Quartus

®

Prime Design Suite: 17.1

2.1.1 Set a High-Speed Target..............................................................................6

2.1.2 Experiment and Iterate................................................................................8

2.1.3 Compile Components Independently..............................................................8

2.1.4 Optimize Sub-Modules.................................................................................9

2.1.5 Avoid Broadcast Signals...............................................................................9

2.2 Hyper-Retiming (Facilitate Register Movement)......................................................... 11

2.2.1 Reset Strategies....................................................................................... 13

2.2.2 Clock Enable Strategies............................................................................. 18

2.2.3 Synthesis Attributes.................................................................................. 19

2.2.4 Timing Constraint Considerations................................................................ 19

2.3.3 Use Registers Instead of Multicycle Exceptions.............................................. 29

2.4 Hyper-Optimization (Optimize RTL)......................................................................... 29

2.4.1 General Optimization Techniques................................................................29

2.4.2 Optimizing Specific Design Structures.......................................................... 41

4.1 Median Filter Design Example................................................................................. 64

4.1.1 Step 1: Compile the Base Design................................................................ 65

4.1.2 Step 2: Add Pipeline Stages and Remove Asynchronous Resets....................... 67

4.1.3 Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets........... 69

5.1.4 Loops...................................................................................................... 85

5.1.5 One Critical Chain per Clock Domain............................................................89

5.1.6 Critical Chains in Related Clock Groups........................................................ 89

5.1.7 Complex Critical Chains............................................................................. 89

5.1.8 Extend to locatable node............................................................................91

5.1.9 Domain Boundary Entry and Domain Boundary Exit....................................... 91

5.1.10 Critical Chains with Dual Clock Memories....................................................93

5.1.11 Critical Chain Bits and Buses.....................................................................94

Contents

Stratix

10 High-Performance Design Handbook

7.1 Design Migration and Performance Exploration........................................................ 101

7.1.1 Black-boxing Verilog HDL Modules............................................................. 102

7.1.2 Black-boxing VHDL Modules......................................................................102

7.1.3 Clock Management.................................................................................. 104

7.1.4 Pin Assignments......................................................................................104

7.1.5 Transceiver Control Logic..........................................................................105

7.1.6 Upgrade Outdated IP Cores...................................................................... 106

7.2 Top-Level Design Considerations........................................................................... 106

8 Appendices.................................................................................................................. 108

8.1 Appendix A: Parameterizable Pipeline Modules........................................................ 109

Intel

®

™

FPGA Architecture Introduction

This document describes design techniques to achieve maximum performance with the

Intel

®

Hyperflex

™

FPGA architecture. This architecture supports new Hyper-Retiming,

Hyper-Pipelining, and Hyper-Optimization design techniques that enable the highest

clock frequencies for Intel Stratix

®

10 devices.

"Registers everywhere” is a key innovation of the Intel Hyperflex FPGA architecture.

Intel Stratix 10 devices pack bypassable Hyper-Registers into every routing segment

in the device core, and at all functional block inputs.

With Intel Stratix 10 bypassable Hyper-Registers, the routing signal can travel through

the register first, or bypass the register direct to the multiplexer. One bit of the FPGA

configuration memory (CRAM) controls this multiplexer.

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

techniques for Intel Stratix 10 designs.

demonstrate performance improvement techniques using real design examples.

Table 1. Glossary

Term/Phrase Description

Critical Chain Any design condition that prevents retiming of registers is the critical

chain. The limiting factor may include more than one register-to-register

path in a chain. The f

MAX

of the critical chain and its associated clock

domain is limited by the average delay of a register-to-register path,

and quantization delays of indivisible circuit elements like routing wires.

Intel Hyperflex FPGA Architecture Intel Stratix 10 device core architecture that includes additional

registers, called Hyper-Registers, everywhere throughout the core fabric.

Hyper-Registers provide increased bandwidth and improved area and

power efficiency.

Hyper-Optimization Design process that improves design performance through

implementation of key RTL changes recommended by Fast Forward

compilation, such as restructuring logic to use functionally equivalent

feed-forward or pre-compute paths, rather than long combinatorial

feedback paths.

Hyper-Pipelining Design process that eliminates long routing delays by adding additional

1 Intel

Intel