UG517 (v5.1) September 21, 2010 www.xilinx.com Virtex-6 FPGA Integrated Block for PCI Express
Revision History
The following table shows the revision history for this document.
Date Version Revision
06/24/09 2.0 Initial Xilinx release.
09/16/09 3.0 Updated core to v1.3 and ISE to v11.3. Updated to add Root Port capability.
12/02/09 4.0 Updated core to v1.4 and ISE to v11.4. Updated to add VHDL support.
04/19/10 5.0
Updated core to v1.5 and ISE to v12.1. Revised references to Gen1 and Gen2 to 2.5 Gb/s and
5.0 Gb/s link speeds. Removed requirement about operation at 5.0 Gb/s data rates needing a
250 MHz clock source from Table 2-5, Clocking, page 184, and System and PCI Express
Interfaces, page 263. Removed notes or text about never asserting trn_rbar_hit_n[6:0] in Root
Port configuration in Table 2-13, page 37, in Basic TLP Receive Operation, page 107, and in
Packet Base Address Register Hit on Receive Transaction Interface, page 115. Changed
“Extended Capability Structure” to “Capability Structure” in the descriptions of
cfg_dstatus[15:0], cfg_dcommand[15:0], cfg_dcommand2[15:0], cfg_lstatus[15:0], and
cfg_lcommand[15:0] in Table 2-17, page 42, Table 6-14, page 155, cfg_dstatus[15:0], page 157,
cfg_dcommand[15:0], page 157, cfg_lstatus[15:0], page 158, cfg_lcommand[15:0], page 158,
and cfg_dcommand2[15:0], page 159.
Chapter 2: In Table 2-2, changed address range 048h through 05Ch to optional, tagged
address range 074h through 080h as Root Port only and divided into four rows, and added
table notes 1 and 2. In Table 2-10, updated the description of trn_clk. In Table 2-14, added
parenthetical text to the 19 encoding of pl_ltssm_state[5:0] on page 39. In Table 2-17, changed
the cfg_byte_en_n[3:0] description to “write access” on page 42. In Table 2-20, removed “is
not used” from cfg_interrupt_do[7:0] description.
Chapter 4: Added content to Running the Simulation. Added reference to Synplicity to step 2,
page 62. Added the implement folder and subfolders to Example Design. Added
introductory paragraph to <project directory>/<component name>.
Chapter 5: Replaced Figure 5-5 and Figure 5-13. Added note on page 71 about screen captures
providing general information. Corrected number of lanes in Table 5-1. Added Buffering
Optimized bullet to Block RAM Configuration Options. Indicated that the De-emphasis field
in the Link Control 2 Register is not editable. Added Disable TX ASPM L0s and Link Number
bullets to Advanced Physical Layer. Removed GT DRP Ports bullet from Debug Ports.
Chapter 6: Changed the PCI Express Base Specification version number to 2.0 in the
introductory paragraph. In Basic TLP Transmit Operation, added bullet and note about user-
implemented Configuration Space requests, and added new paragraph about filtering. In
Table 6-8 and Table 6-9, added table note about TLP. In Design Considerations for a Directed
Link Change, added statement about Link Partner being 5.0 Gb/s (Gen2) capable to sixth
bullet and added new bullet about not initiating a retrain. Added table note defining
checkmarks and X’s in Table 6-35. Added a paragraph about when Per-Vector Masking is
enabled to the end of MSI Mode on page 181.
Chapter 7: In Table 7-1, corrected X0Y8 in x8 column of the FF1759/X0Y0 row. In Table 7-2,
added HX380T to FF1154/X0Y0, FF1154/X0Y1, FF1154/X0Y2, and FF1154/X0Y3 rows; added
HX380T and HX255T to FF1923/X0Y1 row; changed device to HX255T in FF1923/X0Y0 row;
removed FF1923/X0Y1 row; and added table notes 1 and 2.
Chapter 8: Revised Figure 8-1. Added paragraph to the end of Board Power in Real-World
Systems on page 209. Added the Hot Plug Systems and Configuration Time Matrix: Non-
ATX-Based Motherboards sections. Corrected measurement to 250 ms in Successful FPGA
Recognition, page 213.
Added Chapter 9, Known Restrictions.
Appendix A: Added VHDL Test Selection section. Added IUS flow throughout the VHDL
Flow section.
Appendix B: Removed Figure B-3, which was a duplicate of Figure B-2.
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