DDR4 SDRAM SO-DIMM Design Specification
Revision 1.00 Page 5
PROPOSED
Table of Contents
1 Product Description...............................................................................................5
2 Environmental Requirements ...............................................................................6
3 Connector Pinout and Signal Description ...........................................................7
3.1 DDR4 SO-DIMM Connector Pin Assignments ...................................................... 10
4 Power Details........................................................................................................12
4.1 DIMM Voltage Requirements ................................................................................. 12
4.1.1 VTT Range....................................................................................................................12
4.1.2 Load Line.......................................................................................................................12
4.2 Rules for Power-Up Sequence............................................................................... 13
5 Component Details...............................................................................................14
5.1 Component Types and Placement ........................................................................ 17
5.2 Decoupling Guidelines........................................................................................... 17
6 DIMM Design Details............................................................................................18
6.1 Signal Groups ......................................................................................................... 18
6.2 Explanation of Net Structure Diagrams ................................................................ 18
6.3 General Net Structure Routing Rules ................................................................... 19
6.3.1 Clock, Control, and Address/Command Groups ...........................................................19
6.3.2 Lead-in vs. Loaded Sections.........................................................................................20
6.3.3 Length/Delay Matching to SDRAM Devices..................................................................20
6.3.4 Velocity Compensation..................................................................................................21
6.3.5 Load/Delay Compensation............................................................................................21
6.3.6 Data and Strobe Group .................................................................................................21
6.3.7 ALERT_n Wiring............................................................................................................21
6.3.8 Via Compensation.........................................................................................................22
6.3.9 Plane Referencing.........................................................................................................23
6.4 Address Mirroring................................................................................................... 23
6.5 DIMM Routing Space Constraints ......................................................................... 24
6.6 DIMM Physical Requirements................................................................................ 25
6.6.1 Via Size .........................................................................................................................25
6.6.2 Component Pad Sizes and Geometry...........................................................................25
6.6.3 DRAM Package Size.....................................................................................................25
6.6.4 Clock Termination .........................................................................................................25
6.6.5 ZQ Calibration Wiring....................................................................................................25
6.6.6 DQ Stub Resistor ..........................................................................................................26
6.6.7 TEN Wiring ....................................................................................................................26
6.7 Reference Stackups................................................................................................ 26
6.8 Impedance Targets ................................................................................................. 28
6.9 SPD Wiring and Placement.................................................................................... 29
6.10 DQ Mapping to Support CRC................................................................................. 30
7 Serial Presence Detect Component Specification ............................................33
7.1 Serial Presence Detect Definition.......................................................................... 33
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