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Multi-Chip Package MEMORY 2G bit (1.8V) 4bit-ECC NAND Flash and 1G bit (1.8V/1.2V) LPDDR 2
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JSFBAx3YHABBx
2Gb 4bit-ECC NAND FLASH + 1Gb LPDDR2 MCP
Mlti
Chi P k MEMORY
M
u
lti
-
Chi
p
P
ac
k
age
MEMORY
2G bit (1.8V) 4bit-ECC NAND Flash and 1G bit (1.8V/1.2V) LPDDR 2
Revision No. History Draft Date Remark
0.1 Initial Draft 2014.01.23
0.2 Add Package type (162B, 8x10.5x0.8(max)) 2014.02.21
0.3 Revise Typo 2014.03.17
0.4 Add 533MHz Spec 2015.10.21
MCP Product Information
NAND
DRAM
Organization NAND DRAM MCP
Device Name
NAND
Density
DRAM
Density
Combination Package Type
(NAND,DRAM) Version Version Version
JSFBAA3YHABBE-425
B 2Gb A 1Gb
A x8, x16
3
SLC +
LPDDR2
HAB4bit ECC
BE
121 Ball
8x8x0.86
JSFBAC3YHABBE-425 C x16,x16
JSFBAB3YHABBD-425
B 2Gb A 1Gb
B x8, x32
3
SLC +
LPDDR2
HAB4bit ECC
BD
162 Ball
JSFBAD3YHABBD-425 D x16, x32
11.5x13x1.0
JSFBAB3YHABBG-425
B 2Gb A 1Gb
B x8, x32
3
SLC +
LPDDR2
HAB4bit ECC
BG
162 Ball
JSFBAD3YHABBG-425 D x16, x32
8x10.5x0.8
Rev 0.4 / Oct. 2015
Preliminary
1

JSFBAx3YHABBx
2Gb 4bit-ECC NAND FLASH + 1Gb LPDDR2 MCP
Multi-Chi
p
Packa
g
e MEMORY
pg
2G bit (x8,1.8V) 4bit-ECC NAND Flash and 1G bit (x16,1.8V/1.2V) LPDDR2 MCP
2G bit (x8,1.8V) 4bit-ECC NAND Flash and 1G bit (x32,1.8V/1.2V) LPDDR2 MCP
2G bit (x16,1.8V) 4bit-ECC NAND Flash and 1G bit (x16,1.8V/1.2V) LPDDR2 MCP
2G bit (x16,1.8V) 4bit-ECC NAND Flash and 1G bit (x32,1.8V/1.2V) LPDDR2 MCP
<MCP Features>
<MCP Features>
. Operating Temperature : Commercial -0℃ ~ 70℃
Extended -25℃ ~ 85℃
Industrial -40℃ ~ 85℃
. 121 ball FBGA Type : 8.0mm x 8.0mm x 0.86mm(Max.)
. 162 ball FBGA Type : 11.5mm x 13.0mm x 1.0mm(Max.)
. 162 ball FBGA Type : 8.0mm x 10.5mm x 0.80mm(Max.)
<NAND Features>
Additional Features
- 2Gb part support Multi-plane Program and Erase
commands
- Supports Copy Back Program
- 2Gb parts support Multi-plane Copy Back Program
- Supports Read Cache
Electronic Signature
-1
st
cycle : Manufacturer Code
Density
-2Gbit
Architecture
- Input/Output Bus width : 8-bits/16-bits
- Page Size:
-x8
2Gbit :
(
2048 + 128
)
b
y
tes; 128-b
y
te s
p
are area
-2
nd
cycle : Device Code
-3
rd
cycle : Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages,
Interleaved Program, Write Cache
-4
th
cycle : Page size, Block size, Organization,
Spare size, Serial Access Time
-5
th
cycle : ECC, Multi-plane information
Page Read / Program
()y
yp
-x16
2Gbit : (1024 + 64) words; 64-words spare area
- Block Size: 64 Pages
-x8
2Gbit : (128k + 8k) bytes
-x16
2Gbit : (64k + 4k) words
- Plane Size:
8
Page
Read
/
Program
- Random access: 30 μs (Max)
- Sequential access: 45 ns (Min)
- Program time: 300 μs (Typ)
- Multi-plane Program time: 300 μs (Typ)
Block Erase
- Block Erase time: 3.5 ms (Typ)
Block Erase / Multi-plane Erase
–
Block Erase time: 3 5 ms (Typ)
-x
8
2Gbit : 1024 Blocks per Plane or (128M + 8M)bytes
-x16
2Gbit : 1024 Blocks per Plane or (64M + 4M) words
- Device Size:
2Gbit : 2 Plane per Device or 256 Mbyte
NAND Flash Interface
-
Open NAND Flash Interface (ONFI) 1 0 compliant
Block
Erase
time:
3
.
5
ms
(Typ)
Reliability
- 50,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 512 Byte)
- 10 Year Data retention (Typ)
Chip Enable Don’t Care Option
- Simple interface with microcontrollers
Open
NAND
Flash
Interface
(ONFI)
1
.
0
compliant
- Address, Data, and Commands multiplexed
Supply Voltage
- 1.8V device: VCC = 1.7V ~ 1.95V
Security
- One Time Programmable (OTP) area
- Serial number (unique ID)
- Non-volatile protection
Rev 0.4 / Oct. 2015
Preliminary
2

JSFBAx3YHABBx
2Gb 4bit-ECC NAND FLASH + 1Gb LPDDR2 MCP
<1Gb LPDDR2 Features>
• VDD1 = 1.7~1.95V
• VDD2 / VDDCA / VDDQ = 1.14~1.30V
• Data width: x16 / x32
• Clock rate: up to 533MHz
• 4 bit pre-fetch DDR architecture
• 8 internal banks for concurrent operation
• Programmable READ and WRITE latencies (RL / WL)
• Programmable burst lengths : 4, 8 or 16
• Burst Type : Sequential or Interleave
• Auto Precharge option for each burst access
• Per Bank Refresh
• Partial Array Self-Refresh (PASR)
• Deep Power Down Mode (DPD mode)
• Programmable output buffer driver strength
• Data mask (DM) for write data
• Clock Stop capability durin
g
idle periods
• Double data rate for data output
• Differential clock inputs (CK and CK#)
• Bidirectional differential data strobe (DQS and DQS#)
• Commands & addresses entered on both positive and negative CK edges; data and data mask
referenced to both edges of DQS
referenced to both edges of DQS
• No DLL : CK to DQS is not synchronized.
• Edge aligned data output, center aligned data input
• Auto refresh duty cycle : 7.8us for -25 to 85℃
• Interface : HSUL_12
• JEDEC LPDDR2-S24B com
p
liance
p
Rev 0.4 / Oct. 2015
Preliminary
3

JSFBAx3YHABBx
2Gb 4bit-ECC NAND FLASH + 1Gb LPDDR2 MCP
PIN CONFIGURATION(121
FBGA)
PIN CONFIGURATION(121
-
FBGA)
(2Gb NAND Flash x8/x16, 1Gb LPDDR2 x16)
1234567891011
A
NC NC IO2 IO5
V
CCn
V
CCn
V
DD2
V
SS
V
DDQ NC NC
A
B NC VSS IO3 IO6 IO7 VSS VDD1 DQ15 DQ14 VSSQ NC B
C VCCn IO0 IO4 RFU RB# CLE DQ11 DQ12 DQ13 C
D VDD2 IO1 DQ10 VSSQ D
E VSS ZQ CA9 DQ8 DQ9 VDDQ E
F VDD1 CA8 VCCn VSS WE# DQS1 VSSQ F
G VSS CA7 CA6 IO12 RE# CE# DQS1# DM1 VDDQ G
H NC CA5 IO13 IO11 IO9 VREFDQ VDD2 H
J VDD2 VREFCA VSS IO14 IO10 IO8 DQS0# DM0 VDD1 J
K
CK
CK#
IO15
VSS
VCC
DQS0
VDDQ
K
K
CK
CK#
IO15
VSS
VCC
n
DQS0
VDDQ
K
L RFU CS1# RFU DQ7 DQ6 VSSQ L
M CA4 CA3 DQ5 VDDQ M
N NC CA2 CA1 RFU ALE WP# DQ3 DQ2 VSSQ N
P NC
V
SS CA0 RFU CKE1 NC DQ0 DQ1 DQ4
V
SSQ NC P
R NC NC VSS VDD2 VDD1 VSS VDD2 VSS VDDQ NC NC R
1234567891011
NC / RFU NAND NAND (x16) LPDDR 2
Note :
1. IO8~IO15 pins are NC for the x8 NAND device.
2 VSS i h d d
Rev 0.4 / Oct. 2015
Preliminary
4
2
.
VSS
p
i
ns
are
s
h
are
d g
roun
d
3. RFU pins are reserved for future use.

JSFBAx3YHABBx
2Gb 4bit-ECC NAND FLASH + 1Gb LPDDR2 MCP
PIN DESCRIPTION -121B_FBGA
(2Gb NAND Flash x08/x16, 1Gb LPDDR2 x16)
2Gb( x 8/ x16) NAND Flash
SYMBOL DESCRIPTION
IO[7:0] (x8)
IO[15:0] (x16)
Data Input / Output
CE# Chip Enable
WE# Write Enable
RE# Read Enable
ALE Address Latch Enable
CLE Command Latch Enable
WP#
Wit P t t
SYMBOL DESCRIPTION
1Gb(x16) LPDDR2
WP#
W
r
it
e
P
ro
t
ec
t
R/B# Ready/Busy out
VCCn Power Supply
CA[9:0] Command / Address Inputs
CK, CK# Differential Clock Input
CKE1 Clock Enable
CS1# Chip Select
DM[1:0] Data Mask
DQ[15:0] Data Input / Output
DQS[1:0]
DQS#[1:0]
Data Strobe : Coordinates READ/WRITE transfers of data;
One DQS/DQS# pair per DQ byte.
VDD1, VDD2 LPDDR2 power supply 1 and 2
VDDQ LPDDR2 DQ power supply
VREFCA, VREFDQ LPDDR2 reference for CA pins and DQ pins
VSSQ LPDDR2 I/O ground
ZQ
External impedance (240-ohm) : This signal is used to calibrate the
device output impedance.
SYMBOL DESCRIPTION
Common
Rev 0.4 / Oct. 2015
Preliminary
5
VSS Shared ground
NC No connect
RFU Reserved for future use
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