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NXP QorIQ LS1088A Data Sheet
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更新于2023-05-30
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A member of the Layerscape (LS1) series, the LS1088A is a cost-effective, power- efficient, and highly integrated system-on-chip (SoC) device featuring eight extremely power-efficient 64-bit ARM® Cortex®-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. The LS1088A family of devices can be used for enterprise and service provider routers, Virtual CPE, industrial communications, security appliance and military and aerospace applications.
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LS1088A
QorIQ LS1088A Data Sheet
Features
• LS1088A contains eight ARM® Cortex®-A53 (32/64
bit) cores with the following capabilities:
– Speed up to 1.6 GHz
– Arranged as two clusters of four cores
– 32 KB L1 instruction cache (ECC protection) and 32
KB L1 data cache (ECC protection)
– Two 1 MB unified I/D L2 cache (ECC protection),
one per Cortex-A53 core cluster
– NEON™ SIMD coprocessor
– ARMv8 cryptography extensions
• Hierarchical interconnect fabric:
– Hardware-managed data coherency
– Up to 700 MHz operation
• One 32/64-bit DDR4 SDRAM memory controller:
– ECC and interleaving support
– Up to 2.1 GT/s
• Datapath acceleration architecture 2.0 (DPAA2)
incorporates acceleration for the following functions:
– Packet parsing, classification, and distribution
(WRIOP)
– Queue management for scheduling, packet
sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation
and de-allocation (BMan)
– Cryptography acceleration (SEC)
– IEEE 1588 support
– Advanced I/O processor (AIOP)
• Parallel Ethernet interfaces:
– Up to two RGMII interfaces
• Eight SerDes lanes for high-speed peripheral
interfaces:
– Three PCI Express 3.0 controllers (one supporting
x4 operation)
– One serial ATA (SATA 3.0) controller supporting
6 Gbps
– Up to two SGMII supporting 2500 Mbps
– Up to four SGMII supporting 1000 Mbps
– Up to two XFI (10 GbE) interfaces
– Up to two QSGMII
– Supports 1000Base-KX
– Supports 10GBase-KR
• Additional peripheral interfaces include:
– One quad serial peripheral interface (QSPI)
controller, one serial peripheral interface (SPI)
controller
– Integrated flash controller (IFC) supporting NAND
and NOR flash with 28-bit addressing and 16-bit
data
– Two USB 3.0 controllers with integrated PHY
– Enhanced secure digital host controller supporting
SD 3.0, eMMC 4.4, and eMMC 4.5 modes
– uQE supporting TDM/HDLC
– Four I2C controllers
– Two 16550-compliant DUARTs
– General purpose IO (GPIO), four FlexTimers, and
nine watchdog timers
– Trust architecture
– Debug support with run control, data acquisition,
high-speed trace, and performance/event monitoring
• 780 FC-PBGA package, 23 mm x 23 mm, 0.8 mm
pitch
NXP Semiconductors
Document Number LS1088A
Data Sheet: Technical Data
Rev. 0, 01/2018
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.

Table of Contents
1 Overview.............................................................................................. 3
2 Pin assignments....................................................................................3
2.1 780 BGA ball layout diagrams..................................................4
2.2 Pinout list...................................................................................10
3 Electrical characteristics.......................................................................51
3.1 Overall DC electrical characteristics.........................................51
3.2 General AC timing specifications............................................. 57
3.3 Power sequencing......................................................................58
3.4 Power-down requirements.........................................................61
3.5 Power characteristics.................................................................61
3.6 Power-on ramp rate................................................................... 63
3.7 Input clocks............................................................................... 63
3.8 RESET initialization timing specifications............................... 70
3.9 Battery-backed security monitor interface................................ 71
3.10 DDR4 SDRAM controller.........................................................72
3.11 Dual universal asynchronous receiver/transmitter (DUART)
interface..................................................................................... 77
3.12 Enhanced secure digital host controller (eSDHC).....................79
3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588).............87
3.14 General purpose input/output (GPIO) interface........................ 97
3.15 Generic interrupt controller (GIC) interface..............................101
3.16 High-speed serial interfaces (HSSI).......................................... 103
3.17 I2C interface.............................................................................. 144
3.18 Integrated Flash Controller........................................................147
3.19 JTAG interface.......................................................................... 166
3.20 Quad serial peripheral interface (QuadSPI).............................. 169
3.21 QUICC engine specifications....................................................173
3.22 Serial peripheral interface (SPI)................................................ 179
3.23 Universal serial bus (USB) interface.........................................182
4 Hardware design considerations...........................................................185
4.1 Clock ranges..............................................................................185
4.2 Power supply design..................................................................186
5 Thermal................................................................................................ 187
5.1 Recommended thermal model...................................................188
5.2 Temperature diode.....................................................................188
5.3 Thermal management information............................................ 188
6 Package information.............................................................................191
6.1 Package parameters for the FC-PBGA......................................191
6.2 Mechanical dimensions of the FC-PBGA.................................191
7 Security fuse processor.........................................................................193
8 Ordering information............................................................................193
8.1 Part numbering nomenclature....................................................193
8.2 Part marking ............................................................................. 194
9 Revision history....................................................................................195
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
2 NXP Semiconductors

1 Overview
A member of the Layerscape (LS1) series, the LS1088A is a cost-effective, power-
efficient, and highly integrated system-on-chip (SoC) device featuring eight extremely
power-efficient 64-bit ARM® Cortex®-A53 cores with ECC-protected L1 and L2 cache
memories for high reliability, running up to 1.6 GHz.
The LS1088A family of devices can be used for enterprise and service provider routers,
Virtual CPE, industrial communications, security appliance and military and aerospace
applications.
This figure shows the LS1088A block diagram.
Watchpoint
Cross
Trigger
64-bit
DDR4
Memory Controller
Real Time Debug
Perf
Monitor
PCIe 3.0
SATA 3.0
Trace
4-Lane 10 GHz SerDes
Arm Cortex-
A53 64b Cores
SMMUs
CCI-400™ Coherency Fabric
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
uQE
PCIe 3.0
PCIe 3.0
Trust Zone
Power Management
IFC, QuadSPI, SPI
2x DUART
4x I2C, GPIO
Secure Boot
4x FlexTimer
2x USB3.0 w/PHY
SD/SDIO/eMMC
Arm Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
Arm Cortex-
A53 64b Cores
Buffering
Queue /
Buffer
Manager
Buffer
Advanced
IO
Processor
(AIOP)
Security
Engine
(SEC)
DPAA2 Hardware
Management Complex
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
WRIOP
1G 1G 1G 1G
1G 1G 1G 1G
1/10G
1/10G
4-Lane 10 GHz SerDes
Arm®
Cortex
®
A53 64b Core
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
1 MB L2 - Cache
1 MB L2 - Cache
Arm®
Cortex
®
A53 64b Core
qDMA
Figure 1. LS1088A block diagram
2
Pin assignments
NOTE:
Information given in this section is preliminary and is subject to change.
Overview
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
NXP Semiconductors 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
DDRC1 IFC1 UART1 UART2 I2C1
I2C2 I2C DSPI1 ESDHC1 GIC500
Debug SNVS System Control Clocking DDR Clocking
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB3 PHY 1 USB3 PHY 2 USB EMI1 EMI2
EC1 EC2 Power Ground No Connects
SEE DETAIL A SEE DETAIL B
SEE DETAIL C SEE DETAIL D
Figure 2. Complete BGA Map for the LS1088A
Pin assignments
QorIQ LS1088A Data Sheet, Rev. 0, 01/2018
NXP Semiconductors 5
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