ARMv7-M架构参考手册详解

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ARM®v7-M Architecture Reference Manual ARM®v7-M Architecture Reference Manual是ARM公司发布的一份架构参考手册,旨在为开发者提供ARMv7-M架构的详细信息和指南。本手册涵盖了ARMv7-M架构的各种方面,包括指令集、寄存器、内存管理、异常处理、调试等。 **ARMv7-M架构概述** ARMv7-M架构是一种基于RISC(Reduced Instruction Set Computing,精简指令集计算)架构的微处理器架构,旨在提供高性能、低功耗和小尺寸的解决方案。ARMv7-M架构主要用于嵌入式系统、微控制器和其他实时系统。 **指令集** ARMv7-M架构的指令集基于Thumb-2指令集,具有高代码密度和高执行效率。Thumb-2指令集是一种混合指令集,结合了ARM指令集和Thumb指令集的优点。ARMv7-M架构的指令集包括算术逻辑指令、加载存储指令、分支指令、系统指令等。 **寄存器** ARMv7-M架构的寄存器包括通用寄存器、浮点寄存器、程序计数器、堆栈指针寄存器等。通用寄存器用于存储整数值和地址,浮点寄存器用于存储浮点数值。程序计数器用于存储当前执行的指令地址,堆栈指针寄存器用于管理堆栈。 **内存管理** ARMv7-M架构的内存管理机制基于虚拟内存(Virtual Memory)和分页机制。虚拟内存机制允许操作系统将物理内存分配给不同的进程,提高了系统的安全性和可靠性。分页机制将物理内存分割成固定大小的页,提高了内存的使用效率。 **异常处理** ARMv7-M架构的异常处理机制用于处理各种异常情况,例如指令执行错误、内存访问错误、系统调用等。异常处理机制包括异常类型、异常处理程序、异常处理流程等。 **调试** ARMv7-M架构的调试机制用于调试和测试嵌入式系统和微控制器。调试机制包括指令追踪、寄存器监视、断点设置、单步执行等功能。 **许可和版权** ARMv7-M Architecture Reference Manual的版权归ARM有限公司所有。任何人不得复制、修改、分发或使用本手册的任何部分,除非获得ARM有限公司的书面许可。
2016-12-29 上传
This manual describes the ARM® architecture v8, ARMv8. The architecture describes the operation of an ARMv8-A Processing element (PE), and this manual includes descriptions of: • The two Execution states, AArch64 and AArch32. • The instruction sets: — In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the ARM architecture. — In AArch64 state, the A64 instruction set. • The states that determine how a PE operates, including the current Exception level and Security state, and in AArch32 state the PE mode. • The Exception model. • The interprocessing model, that supports transitioning between AArch64 state and AArch32 state. • The memory model, that defines memory ordering and memory management. This manual covers a single architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA). • The programmers’ model, and its interfaces to System registers that control most PE and memory system features, and provide status information. • The Advanced SIMD and floating-point instructions, that provide high-performance: — Single-precision and double-precision floating-point operations. — Conversions between double-precision, single-precision, and half-precision floating-point values. — Integer, single-precision floating-point, and in A64, double-precision vector operations in all instruction sets. — Double-precision floating-point vector operations in the A64 instruction set. • The security model, that provides two security states to support secure applications. • The virtualization model, that support the virtualization of Non-secure operation. • The Debug architecture, that provides software access to debug features.