QuartusII18.0用户推荐设计指南_LPMquartus18MegawigardPlugInmanager

Quartus

需积分: 50 121 浏览量更新于2023-05-31 评论收藏 789KB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

Design Recommendations User

Guide

Intel

Quartus

Prime Pro Edition

Updated for Intel

Quartus

Prime Design Suite: 18.0

Send Feedback

UG-20131 | 2018.05.07

Latest document on the web: PDF | HTML

Contents

1. Recommended HDL Coding Styles .................................................................................. 4

1.1. Using Provided HDL Templates................................................................................ 4

1.1.1. Inserting HDL Code from a Provided Template............................................... 4

1.2. Instantiating IP Cores in HDL.................................................................................. 5

1.3. Inferring Multipliers and DSP Functions.....................................................................6

1.3.1. Inferring Multipliers....................................................................................6

1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions........................... 7

1.4. Inferring Memory Functions from HDL Code ............................................................. 8

1.4.1. Inferring RAM functions from HDL Code........................................................ 9

1.4.2. Inferring ROM Functions from HDL Code..................................................... 26

1.4.3. Inferring Shift Registers in HDL Code..........................................................28

1.5. Register and Latch Coding Guidelines..................................................................... 31

1.5.1. Register Power-Up Values..........................................................................31

1.5.2. Secondary Register Control Signals Such as Clear and Clock Enable................33

1.5.3. Latches ..................................................................................................34

1.6. General Coding Guidelines.................................................................................... 37

1.6.1. Tri-State Signals ..................................................................................... 38

1.6.2. Clock Multiplexing.................................................................................... 38

1.6.3. Adder Trees ............................................................................................40

1.6.4. State Machine HDL Guidelines................................................................... 41

1.6.5. Multiplexer HDL Guidelines .......................................................................47

1.6.6. Cyclic Redundancy Check Functions ...........................................................49

1.6.7. Comparator HDL Guidelines.......................................................................52

1.6.8. Counter HDL Guidelines............................................................................ 53

1.7. Designing with Low-Level Primitives....................................................................... 53

1.8. Document Revision History ...................................................................................54

2. Recommended Design Practices................................................................................... 56

2.1. Following Synchronous FPGA Design Practices..........................................................56

2.1.1. Implementing Synchronous Designs........................................................... 56

2.1.2. Asynchronous Design Hazards................................................................... 57

2.2. HDL Design Guidelines..........................................................................................58

2.2.1. Considerations for the Intel Hyperflex FPGA Architecture............................... 58

2.2.2. Optimizing Combinational Logic................................................................. 59

2.2.3. Optimizing Clocking Schemes.................................................................... 61

2.2.4. Optimizing Physical Implementation and Timing Closure................................67

2.2.5. Optimizing Power Consumption..................................................................69

2.2.6. Managing Design Metastability...................................................................69

2.3. Use Clock and Register-Control Architectural Features...............................................70

2.3.1. Use Global Reset Resources.......................................................................70

2.3.2. Use Global Clock Network Resources.......................................................... 79

2.3.3. Use Clock Region Assignments to Optimize Clock Constraints.........................80

2.3.4. Avoid Asynchronous Register Control Signals............................................... 82

2.4. Implementing Embedded RAM............................................................................... 83

2.5. Document Revision History....................................................................................83

3. Managing Metastability with the Intel Quartus Prime Software.................................... 86

3.1. Metastability Analysis in the Intel Quartus Prime Software.........................................87

Contents

Design Recommendations User Guide Intel

Quartus

Prime Pro Edition

3.1.1. Synchronization Register Chains................................................................ 87

3.1.2. Identify Synchronizers for Metastability Analysis.......................................... 88

3.1.3. How Timing Constraints Affect Synchronizer Identification and

Metastability Analysis............................................................................... 88

3.2. Metastability and MTBF Reporting...........................................................................89

3.2.1. Metastability Reports................................................................................ 90

3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation...................................... 92

3.3. MTBF Optimization............................................................................................... 92

3.3.1. Synchronization Register Chain Length....................................................... 93

3.4. Reducing Metastability Effects................................................................................94

3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer.....94

3.4.2. Force the Identification of Synchronization Registers.....................................94

3.4.3. Set the Synchronizer Data Toggle Rate........................................................95

3.4.4. Optimize Metastability During Fitting.......................................................... 95

3.4.5. Increase the Length of Synchronizers to Protect and Optimize........................95

3.4.6. Increase the Number of Stages Used in Synchronizers.................................. 95

3.4.7. Select a Faster Speed Grade Device............................................................96

3.5. Scripting Support.................................................................................................96

3.5.1. Identifying Synchronizers for Metastability Analysis...................................... 96

3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation...................................... 97

3.5.3. report_metastability and Tcl Command....................................................... 97

3.5.4. MTBF Optimization................................................................................... 97

3.5.5. Synchronization Register Chain Length....................................................... 98

3.6. Managing Metastability......................................................................................... 98

3.7. Document Revision History....................................................................................98

A. Intel Quartus Prime Pro Edition User Guides.............................................................. 100

Contents

Design Recommendations User Guide Intel

Quartus

Prime Pro Edition

1. Recommended HDL Coding Styles

This chapter provides Hardware Description Language (HDL) coding style

recommendations to ensure optimal synthesis results when targeting Intel FPGA

devices.

HDL coding styles have a significant effect on the quality of results for programmable

logic designs. Synthesis tools optimize HDL code for both logic utilization and

performance; however, synthesis tools cannot interpret the intent of your design.

Therefore, the most effective optimizations require conformance to recommended

coding styles.

Note: For style recommendations, options, or HDL attributes specific to your synthesis tool

(including other Quartus software products and other EDA tools), refer to the

synthesis tool vendor’s documentation.

Related Information

• Advanced Synthesis Cookbook

• Design Examples

• Reference Designs

1.1. Using Provided HDL Templates

The Intel Quartus Prime software provides templates for Verilog HDL, SystemVerilog,

and VHDL templates to start your HDL designs. Many of the HDL examples in this

document correspond with the Full Designs examples in the Intel Quartus Prime

Templates. You can insert HDL code into your own design using the templates or

examples.

1.1.1. Inserting HDL Code from a Provided Template

Click File ➤ New.

2. In the New dialog box, select the type of design file corresponding to the type of

HDL you want to use: SystemVerilog HDL File, VHDL File, or Verilog HDL

File; and click OK. A text editor tab with a blank file opens.

3. Right-click the blank file, and click Insert Template....

4. In the Insert Template dialog box, expand the section corresponding to the

appropriate HDL, then expand the Full Designs section.

5. Select a template. The HDL appears in the Preview pane.

6. To paste the HDL design into the blank Verilog or VHDL file you created, click

Insert.

7. Close the Insert Template dialog box by clicking Close.

UG-20131 | 2018.05.07

and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other

countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

剩余100页未读，继续阅读

云游西京

粉丝: 1
资源: 12

会员权益专享

Quartus II 18.0 用户推荐设计指南

评论0

会员权益专享

最新资源

Quartus II 18.0 用户推荐设计指南

评论0

quartus ii 18.0安装包

使用Verilog设计的Quartus II入门指南

quartus ii18.0的波形仿真

quartus ii18.0如何仿真

quartus ii18.0安装教程

quartus prime18.0安装教程

quartus ii模10计数器设计

quartus ii使用教程vhdl

quartus ii中怎样设计rom

quartus ii与modelsim仿真

quartus ii signaltap用法

quartus ii20.1安装教程

基于quartus ii的交通灯设计

quartus ii14.0安装教程

quartus ii 13.1使用教程

quartus ii打不开qpf文件

quartus ii 11.0安装教程

quartus ii 13.1器件库安装

quartus ii license

怎么卸载quartus ii 13.0

会员权益专享

最新资源