Altera Corporation 1
AN-428-1.1 Preliminary
Application Note 428
MAX II CPLD
Design Guidelines
Introduction
With the flexibility of complex programmable logic devices (CPLDs),
together with their low power consumption and low cost, more designers
are using CPLDs in their system design. Using MAX
®
II CPLDs in your
design can be very straightforward when you have some guidelines to
follow, even if you are not a frequent CPLD user. This application note
aims to provide the necessary guidelines on using MAX II devices in your
design, and help you avoid some of the problems users frequently face.
The design guidelines in this application note are categorized under the
following sections:
■ “CPLD Selection” on page 1
■ “Hardware Setup Checklist” on page 3
■ “Design Checklist” on page 12
■ “Additional Development Tools and References” on page 18
f For detailed information about the MAX II device specification, refer to
the MAX II Device Handbook.
CPLD Selection
The MAX II CPLD family offers various device densities to cater to
different user needs. Here are some factors you should consider when
choosing the MAX II device:
■ Number of user I/Os and package offerings
■ Logic density
■ V
CCINT
and power consumption
■ Temperature grade
Number of User I/Os and Package Offerings
The MAX II family has a maximum of 272 input/output (I/O) pins. The
devices are available in various packages and are suitable for different
board requirements. The MAX II Micro FineLine BGA packages are
designed for portable applications, where space-saving is important.
MAX II devices support vertical migration within the same package,
allowing an easy switch between different device densities. Table 1 shows
the packages and the number of user I/O pins available for MAX II
devices.
December 2007, Ver 1.1
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