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MAX II CPLD 设计指南.pdf
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MAX II CPLD Design Guidelines，用于CPLD开发使用。
Altera Corporation 1
Application Note 428
MAX II CPLD
With the flexibility of complex programmable logic devices (CPLDs),
together with their low power consumption and low cost, more designers
are using CPLDs in their system design. Using MAX
II CPLDs in your
design can be very straightforward when you have some guidelines to
follow, even if you are not a frequent CPLD user. This application note
aims to provide the necessary guidelines on using MAX II devices in your
design, and help you avoid some of the problems users frequently face.
The design guidelines in this application note are categorized under the
■ “CPLD Selection” on page 1
■ “Hardware Setup Checklist” on page 3
■ “Design Checklist” on page 12
■ “Additional Development Tools and References” on page 18
f For detailed information about the MAX II device specification, refer to
the MAX II Device Handbook.
The MAX II CPLD family offers various device densities to cater to
different user needs. Here are some factors you should consider when
choosing the MAX II device:
■ Number of user I/Os and package offerings
■ Logic density
and power consumption
■ Temperature grade
Number of User I/Os and Package Offerings
The MAX II family has a maximum of 272 input/output (I/O) pins. The
devices are available in various packages and are suitable for different
board requirements. The MAX II Micro FineLine BGA packages are
designed for portable applications, where space-saving is important.
MAX II devices support vertical migration within the same package,
allowing an easy switch between different device densities. Table 1 shows
the packages and the number of user I/O pins available for MAX II
December 2007, Ver 1.1
2 Altera Corporation
MAX II CPLD Design Guidelines
MAX II CPLDs have 240 to 2,210 logic elements (LEs), or typically 192 to
1,700 equivalent macrocells for you to implement different functions. For
example, the EPM240 device has 240 LEs; this means it has 240 registers
available in the device.
and Power Consumption
MAX II devices support 3.3 V or 2.5 V for V
. The devices have an
internal linear voltage regulator, which regulates the external supply
voltages to the internal operating voltage of 1.8 V. The MAX IIG and
MAX IIZ devices do not use an internal voltage regulator, thus the
devices operate at 1.8-V V
Devices with lower V
total power consumption.
f For more information about the low power applications for MAX II
devices, refer to AN 422: Power Management in Portable Systems Using
MAX II CPLDs.
Table 1. MAX II Packages and User I/O Pins
—808080—— — ——
— 76 76 76 116 — 160 160 —
— — — — 116 — 212 212 —
— — — — — — — 204 272
EPM240Z 54 80 — — — — — — —
EPM570Z — 76 — — — 116 160 — —
Note to Ta bl e 1 :
(1) Packages available in lead-free versions only.
Altera Corporation 3
Hardware Setup Checklist
The MAX II family offers three different temperature grades: commercial,
industrial, and extended temperature grades. Select the correct
temperature grade according to your application. Table 2 shows the
operating temperature range for devices of the three temperature grades.
f For detailed information and specifications of the MAX II device family,
refer to the MAX II Device Handbook.
This section lists some of the items you should check when considering
your hardware setup.
■ “VCCINT and VCCIO Voltages” on page 4
■ “Power-Up Sequencing” on page 4
■ “Input Pin Connection” on page 4
■ “Unused Pin Connection” on page 5
■ “Input Pin Voltages” on page 5
■ “Output Pin Source Current” on page 6
■ “JTAG Pins Pull Up/Down” on page 6
■ “JTAG Chain Connection for Programming” on page 7
■ “JTAG Chain Containing Devices with Different VCCIO” on page 7
■ “JTAG Signal Buffering” on page 8
■ “Device Output-Enable Pin” on page 9
■ “Chip-Wide Reset” on page 10
■ “Register Power-Up Level” on page 10
■ “Latch-Up Prevention” on page 11
Table 2. MAX II Device Operating Temperature Range Note (1)
Commercial 0 85 °C
Industrial –40 100 °C
Automotive –40 125 °C
Note to Ta b le 2 :
(1) MAX IIZ devices are available only in commercial grade.
4 Altera Corporation
MAX II CPLD Design Guidelines
Ensure that the device is powered up within the recommended operating
voltage range. Do not leave any V
, or ground pins
unconnected as this can cause current leakage. V
of all I/O banks and
of the device must be fully powered up, not only for normal
operation, but also for in-system programming (ISP).
The MAX II family has the MultiVolt™ core and I/O features. The
MultiVolt core feature allows the device to support different V
voltages. The MAX II device accepts 2.5-V or 3.3-V V
, while MAX IIG
and MAX IIZ devices accept 1.8-V V
. The MultiVolt I/O feature
allows the device to support 1.5-V, 1.8-V, 2.5-V, and 3.3-V V
Each I/O bank is powered up individually by the VCCIO pins of that
particular bank, and is independent of the V
of other I/O banks.
f For information about the power regulation for MAX II devices, refer to
Power Management Reference Guide for Altera FPGAs & CPLDs at
MAX II devices support hot-socketing. They are designed to operate in
multiple-voltage environments, so they can tolerate any power-up
sequence. You can either power up V
first, or both at the
same time. Input signals of 3.3, 2.5, 1.8, or 1.5 V can drive the devices
without special precautions before V
is applied. Normal
operation does not occur until both power supplies are in their
recommended operating range.
f The MAX II I/O Characteristics During Hot Socketing white paper shows
the I/O pin characteristics for different power-up sequences.
Input Pin Connection
All input pins of your design should be driven by either V
This is because floating input pins have undefined values and your
design may not work correctly with those undefined input values.
Floating input pins also cause additional noise going into the device. This
applies to bidirectional pins functioning as input pins as well.
Altera Corporation 5
Hardware Setup Checklist
Unused Pin Connection
II software generates the pin report file (.pin) when you
compile your design. This report file specifies how you should connect
the unused pins of your device. For a MAX II device, unused I/O pins are
marked in the report file as either:
depending on how you set the unused pins in the Quartus II software.
All I/O pins specified as GND* can either be connected to ground to
improve the device's immunity to noise or left unconnected. Leave all
RESERVED I/O pins unconnected on your board because these I/O pins
drive out unspecified signals. Tying a RESERVED I/O pin to V
or another signal source can create contention that can damage the output
driver of the device.
RESERVED_INPUT I/O pins can be connected to a high or low signal on
the board while RESERVED_INPUT_WITH_WEAK_PULLUP and
RESERVED_INPUT_WITH_BUS_HOLD pins can be left unconnected.
Input Pin Voltages
The voltage level of the input signal should meet the high-level (V
) input voltages of the device. The input pin may not
recognize the input signal correctly if the voltage level of the signal falls
between the minimum of V
and maximum of V
. Also, do not drive the
pin outside the recommended input voltage (V
) range (-0.5 V to 4 V).
The MultiVolt I/O feature allows the device to interface with systems of
different supply voltages. Each I/O bank is powered up independently
by the VCCIO pins of that bank. Assign the pins that work with the same
voltage level in the same I/O bank so that you can use the other I/O
banks for other V
f For more information about using a MAX II device in a multi-voltage
system, refer to the Using MAX II Devices in Multi-Voltage Systems
chapter of the MAX II Device Handbook.
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