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合泰LCD液晶驱动芯片资料
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更新于2023-05-27
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HT1622 是 128 点 内存映象和多功能的 LCD 驱动器 HT1621 的软件配置特性使它适 用于多种 LCD 应用场合 包括 LCD 模块和显示子系统 用于连接主控制器和 HT1621 的管 脚只有 4 或 5 条 HT1621 还有一个节电命令用于降低系统功耗
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HT1622
RAM Mapping 32´8 LCD Controller for I/O mC
Selection Table
HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM 44
8
888161616
SEG 32 32
32
32 48 64 48 64 64
Built-in Osc.
Ö Ö ÖÖÖÖ
Crystal Osc.
Ö Ö Ö ÖÖÖ Ö
1 April 21, 2000
General Description
HT1622 is a peripheral device specially de
-
signed for I/O type mC used to expand the dis
-
play capability. The max. display segment of
the device are 256 patterns (32´8). It also sup
-
ports serial interface, buzzer sound, Watchdog
Timer or time base timer functions. The
HT1622 is a memory mapping and multi-func
-
tion LCD controller. The software configuration
feature of the HT1622 make it suitable for mul
-
tiple LCD applications including LCD modules
and display subsystems. Only three lines are
required for the interface between the host con
-
troller and the HT1622. The HT162X series
have many kinds of products that match vari
-
ous applications.
Features
·
Operating voltage: 2.7V~5.2V
·
Built-in RC oscillator
·
1/4 bias, 1/8 duty, frame frequency is 64Hz
·
Max. 32´8 patterns, 8 commons, 32 segments
·
Built-in internal resistor type bias generator
·
3-wire serial interface
·
8 kinds of time base/WDT selection
·
Time base or WDT overflow output
·
Built-in LCD display RAM
·
R/W address auto increment
·
Two selectable buzzer frequencies
(2kHz/4kHz)
·
Power down command reduces power
consumption
·
Software configuration feature
·
Data mode and Command mode instructions
·
Three data accessing modes
·
VLCD pin to adjust LCD operating voltage
·
Cascade application

Block Diagram
Pin Assignment
HT1622
2 April 21, 2000
SEG12
NC
SEG8
SEG9
SEG10
SEG11
NC
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
NC
NC
NC
NC
SEG7
56
57
58
59
60
61
62
63
64
52
53
54
55
23
20
21
22
24
25
26
27
28
29
30
31
32
41
51
37
38
39
40
49
48
47
46
45
44
43
42
50
33
34
35
36
H T1622
-
64 Q FP
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
NC
SEG20
SEG21
SEG22
CS
BZ
NC
RD
WR
DATA
VSS
OSCI
VDD
VLCD
IR Q
NC
BZ
T1
T2
COM1
NC
T3
COM0
COM5
COM2
COM3
COM4
COM6
COM7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
1
11
2
3
4
5
6
7
8
9
10
12
13
14
15
18
19
16
17
W atchdog Tim er
and
Tim e B ase G enerator
D isplay R A M
LC D D river/
Bias Circuit
C ontrol
and
Tim ing
Circuit
DATA
WR
OSCI
CS
RD
COM 0
COM 7
SEG 0
SEG 31
Tone Frequency
G enerator
BZ
BZ
IR Q
VSS
VDD
VLCD

Pad Assignment
Chip size: 149 ´ 155 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1622
3 April 21, 2000
BZ
WR
RD
1
28
2
29
3
30
4
31
5
32
6
33
7
34
8
35
9
36
10
37
11
38
12
39
13
40
14
41
15
42
16
43
17
44
18
45
19
46
20
47
21
48
22
49
23
50
24
51
25
52
26
53
27
54
(0 ,0 )
DATA
VSS
OSCI
VDD
VLCD
BZ
T1
T2
T3
COM 0
COM 1
CS
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG 31
SEG 30
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
SEG 20
IR Q

Pad Coordinates Unit: mil
Pad No. X Y Pad No. X Y
1
-68.43
71.78 28 48.15
-71.91
2
-68.43
59.46 29 54.78
-71.91
3
-68.43
52.83 30 69.32
-10.67
4
-69.19
39.14 31 69.32
-4.04
5
-69.36
23.89 32 69.32 2.59
6
-69.36
16.32 33 69.32 9.22
7
-69.36
9.69 34 69.32 15.85
8
-69.36
3.06 35 69.32 22.48
9
-69.36 -3.57
36 69.32 29.11
10
-69.36 -16.92
37 69.32 35.74
11
-69.36 -33.83
38 69.32 42.37
12
-69.36 -43.52
39 69.32 49.00
13
-69.36 -50.15
40 69.32 55.63
14
-69.36 -56.78
41 69.32 62.26
15
-69.36 -63.41
42 69.32 68.89
16
-69.36 -70.04
43 14.19 71.78
17
-39.23 -71.14
44 7.57 71.78
18
-32.60 -71.14
45 0.94 71.78
19
-20.19 -71.14
46
-5.70
71.78
20
-13.56 -71.14
47
-12.32
71.78
21
-1.15 -71.14
48
-18.95
71.78
22 5.48
-71.14
49
-25.58
71.78
23 15.00
-71.91
50
-32.22
71.78
24 21.63
-71.91
51
-38.85
71.78
25 28.26
-71.91
52
-45.47
71.78
26 34.89
-71.91
53
-52.10
71.78
27 41.52
-71.91
54
-58.74
71.78
HT1622
4 April 21, 2000
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