友晶DE5-net板卡使用说明

1.1 GENERAL DESCRIPTION ............................................................................................................................................ 4

1.2 KEY FEATURES .......................................................................................................................................................... 5

1.3 BLOCK DIAGRAM ...................................................................................................................................................... 6

2.1 BOARD OVERVIEW .................................................................................................................................................. 10

2.2 CONFIGURATION, STATUS AND SETUP ..................................................................................................................... 11

2.3 GENERAL USER INPUT/OUTPUT .............................................................................................................................. 14

2.4 TEMPERATURE SENSOR AND FAN CONTROL ............................................................................................................ 18

2.5 CLOCK CIRCUIT ...................................................................................................................................................... 19

2.12 SATA .................................................................................................................................................................... 44

3.1 INTRODUCTION ....................................................................................................................................................... 48

3.2 GENERAL DESIGN FLOW ......................................................................................................................................... 49

3.3 USING SYSTEM BUILDER ........................................................................................................................................ 50

4.1 CFI FLASH MEMORY MAP ...................................................................................................................................... 57

4.2 FPGA CONFIGURE OPERATION ............................................................................................................................... 58

4.3 FLASH PROGRAMMING WITH USERS DESIGN .......................................................................................................... 58

4.4 RESTORE FACTORY SETTINGS ................................................................................................................................. 60

6.2 DDR3 SDRAM TEST ............................................................................................................................................. 81

6.3 DDR3 SDRAM TEST BY NIOS II ............................................................................................................................ 83

7.1 PCI EXPRESS SYSTEM INFRASTRUCTURE ................................................................................................................ 87

7.2 FPGA PCI EXPRESS SYSTEM DESIGN ..................................................................................................................... 88

7.3 PC PCI EXPRESS SYSTEM DESIGN .......................................................................................................................... 93

7.4 FUNDAMENTAL COMMUNICATION ......................................................................................................................... 105

7.5 EXAMPLE 2: IMAGE PROCESS APPLICATION .......................................................................................................... 110

8.1 TEST CODE ............................................................................................................................................................ 115

8.2 LOOPBACK FIXTURE ............................................................................................................................................. 115

8.3 TESTING ................................................................................................................................................................ 117

The Terasic DE5-Net Stratix V GX FPGA Development Kit provides the ideal hardware solution

for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency

communication, and power efficiency. With a full-height, 3/4-length form-factor package, the

DE5-Net is designed for the most demanding high-end applications, empowered with the

top-of-the-line Altera Stratix V GX, delivering the best system-level integration and flexibility in

the industry.

The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps,

high-speed parallel flash memory, and four SATA ports. The feature-set of the DE5-Net fully

supports all high-intensity applications such as low-latency trading, cloud computing,

high-performance computing, data acquisition, network processing, and signal processing.

The following hardware is implemented on the DE5-Net board:

 FPGA

 Clock System

 Memory