Foreword
CMOS scaling has entered the sub-20nm era. This enables the design of system-on-
a-chip containing more than ten billion transistors. However, nanometre level device
physics also causes a plethora of new challenges that percolate all the way up to the
system level. Therefore, system-on-a-chip design is essentially teamwork requiring
a close dialogue between system designers, software engineers, chip architects,
intellectual property providers, and process and device engineers. This is hardly
possible without a common understanding of the nanometre CMOS medium, its
terminology, its future opportunities and possible pitfalls. This is what this book
provides.
It is a greatly extended and revised version of the previous edition. So besides
the excellent coverage of all basic aspects of MOS devices, circuits and systems, it
leads the reader into the novel intricacies resulting from scaling CMOS towards the
sub-10 nm level. This new edition contains updates and additional information on
the issues of increased leakage power and its mitigation, to strain induced mobility
enhancement. Immersion and double patterning litho and extreme UV and other
alternative litho approaches for sub-20 nm are extensively discussed together with
their impact on circuit layout. The design section now also extensively covers
design techniques for improved robustness, yield and manufacturing in view of
increased device variability, soft errors and decreased reliability when reaching
atomic dimensions. Both devices and ICs have entered the 3D era. This is reflected
by discussions on FinFETs, gate-all-around transistors, 3D memories and stacked
memory dies and 3D packaging to fully enable system-in-a-package solutions.
Finally, the author shares his thoughts on the challenges of further scaling when
approaching the end of the CMOS roadmap somewhere in the next decade.
This book is unique in that it covers in a very comprehensive way all aspects of
the trajectory from state-of-the-art process technology to the design and packaging
of robust and testable systems in nanometre scale CMOS. It is the reflection
of the author’s own research in this domain but also of more than 35 years of
experience in training the full CMOS chip development chain to more than 4500
semiconductor professionals at Philips, NXP, ASML, Infineon, ST Microelectron-
ics, TSMC, Applied Materials, IMEC, etc. It provides context and perspective to all
semiconductor disciplines.
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