AlteraIP核应用解析_alteraspi核发送数据

需积分: 10 215 浏览量更新于2023-05-22 评论收藏 3.1MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源详情

资源评论

资源推荐

Embedded Peripheral IP User Guide

Send Feedback

UG-01085

2014.24.07

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Contents

Introduction........................................................................................................ 1-1

Tool Support.................................................................................................................................................1-1

Obsolescence.................................................................................................................................................1-1

Device Support.............................................................................................................................................1-2

Document Revision History.......................................................................................................................1-2

SDRAM Controller Core.....................................................................................2-1

Core Overview..............................................................................................................................................2-1

Functional Description............................................................................................................................... 2-1

Avalon-MM Interface......................................................................................................................2-2

Off-Chip SDRAM Interface............................................................................................................2-2

Board Layout and Pinout Considerations....................................................................................2-3

Performance Considerations..........................................................................................................2-4

Configuration............................................................................................................................................... 2-4

Memory Profile Page.......................................................................................................................2-5

Timing Page......................................................................................................................................2-6

Hardware Simulation Considerations.......................................................................................................2-7

SDRAM Controller Simulation Model.........................................................................................2-7

SDRAM Memory Model.................................................................................................................2-7

Example Configurations............................................................................................................................. 2-8

Software Programming Model...................................................................................................................2-9

Clock, PLL and Timing Considerations................................................................................................... 2-9

Factors Affecting SDRAM Timing................................................................................................2-9

Symptoms of an Untuned PLL.....................................................................................................2-10

Estimating the Valid Signal Window..........................................................................................2-10

Example Calculation......................................................................................................................2-11

Document Revision History.....................................................................................................................2-13

Tri-State SDRAM................................................................................................ 3-1

Feature Description..................................................................................................................................... 3-1

Block Diagram..................................................................................................................................3-2

Configuration Parameter............................................................................................................................3-2

Memory Profile Page.......................................................................................................................3-2

Timing Page......................................................................................................................................3-2

Interface.........................................................................................................................................................3-3

Reset and Clock Requirements.................................................................................................................. 3-8

Architecture..................................................................................................................................................3-8

Avalon-MM Slave Interface and CSR........................................................................................... 3-9

Block Level Usage Model................................................................................................................3-9

Document Revision History.....................................................................................................................3-10

TOC-2

Altera Corporation

Compact Flash Core............................................................................................ 4-1

Core Overview..............................................................................................................................................4-1

Functional Description............................................................................................................................... 4-1

Required Connections.................................................................................................................................4-2

Software Programming Model...................................................................................................................4-3

HAL System Library Support.........................................................................................................4-3

Software Files....................................................................................................................................4-3

Register Maps................................................................................................................................... 4-4

Document Revision History.......................................................................................................................4-5

Common Flash Interface Controller Core..........................................................5-1

........................................................................................................................................................................ 5-1

Core Overview..............................................................................................................................................5-1

Functional Description............................................................................................................................... 5-2

Configuration............................................................................................................................................... 5-2

Attributes Page.................................................................................................................................5-2

Timing page......................................................................................................................................5-3

Software Programming Model...................................................................................................................5-3

HAL System Library Support.........................................................................................................5-4

Software Files....................................................................................................................................5-4

Document Revision History.......................................................................................................................5-4

EPCS Serial Flash Controller Core..................................................................... 6-1

Core Overview..............................................................................................................................................6-1

Functional Description............................................................................................................................... 6-2

Avalon-MM Slave Interface and Registers...................................................................................6-3

Configuration..............................................................................................................................................6-4

Software Programming Model...................................................................................................................6-4

HAL System Library Support.........................................................................................................6-4

Software Files....................................................................................................................................6-5

Document Revision History.......................................................................................................................6-5

JTAG UART Core................................................................................................7-1

Core Overview..............................................................................................................................................7-1

Functional Description............................................................................................................................... 7-1

Avalon Slave Interface and Registers.............................................................................................7-2

Read and Write FIFOs.....................................................................................................................7-2

JTAG Interface................................................................................................................................. 7-2

Host-Target Connection.................................................................................................................7-2

Configuration............................................................................................................................................... 7-3

Configuration Page..........................................................................................................................7-3

Simulation Settings..........................................................................................................................7-4

Hardware Simulation Considerations.......................................................................................................7-5

Software Programming Model...................................................................................................................7-5

TOC-3

Altera Corporation

HAL System Library Support.........................................................................................................7-5

Software Files....................................................................................................................................7-8

Accessing the JTAG UART Core via a Host PC..........................................................................7-9

Register Map.....................................................................................................................................7-9

Interrupt Behavior.........................................................................................................................7-10

Document Revision History.....................................................................................................................7-11

UART Core..........................................................................................................8-1

Core Overview..............................................................................................................................................8-1

Functional Description............................................................................................................................... 8-1

Avalon-MM Slave Interface and Registers...................................................................................8-2

RS-232 Interface...............................................................................................................................8-2

Transmitter Logic.............................................................................................................................8-2

Receiver Logic...................................................................................................................................8-2

Baud Rate Generation..................................................................................................................... 8-3

Instantiating the Core..................................................................................................................................8-3

Configuration Settings.................................................................................................................... 8-3

Simulation Settings..........................................................................................................................8-6

Simulation Considerations.........................................................................................................................8-7

Software Programming Model...................................................................................................................8-7

HAL System Library Support.........................................................................................................8-7

Software Files..................................................................................................................................8-11

Register Map...................................................................................................................................8-11

Interrupt Behavior.........................................................................................................................8-16

Document Revision History.....................................................................................................................8-16

16550 UART........................................................................................................ 9-1

Core Overview..............................................................................................................................................9-1

Feature Description..................................................................................................................................... 9-1

Unsupported Features.....................................................................................................................9-2

Interface.............................................................................................................................................9-2

General Architecture....................................................................................................................... 9-4

Configuration Parameters.............................................................................................................. 9-4

DMA Support...................................................................................................................................9-5

FPGA Resource Usage.....................................................................................................................9-5

Timing and Fmax.............................................................................................................................9-6

Avalon-MM Slave............................................................................................................................ 9-7

Overrun/Underrun Conditions.....................................................................................................9-8

Hardware Auto Flow-Control........................................................................................................9-9

Clock and Baud Rate Selection.................................................................................................... 9-10

Software Programming Model.................................................................................................................9-10

Overview......................................................................................................................................... 9-10

Supported Features........................................................................................................................9-10

Unsupported Features...................................................................................................................9-11

Configuration.................................................................................................................................9-11

16550 UART API...........................................................................................................................9-12

Driver Examples.............................................................................................................................9-16

TOC-4

Altera Corporation

Document Revision History.....................................................................................................................9-20

SPI Core.............................................................................................................10-1

Core Overview............................................................................................................................................10-1

Functional Description............................................................................................................................. 10-1

Example Configurations...............................................................................................................10-2

Transmitter Logic.......................................................................................................................... 10-2

Receiver Logic.................................................................................................................................10-3

Master and Slave Modes............................................................................................................... 10-3

Avalon-MM Interface....................................................................................................................10-5

Configuration.............................................................................................................................................10-5

Master/Slave Settings.....................................................................................................................10-5

Data Register Settings....................................................................................................................10-6

Timing Settings.............................................................................................................................. 10-6

Software Programming Model.................................................................................................................10-7

Hardware Access Routines...........................................................................................................10-7

Software Files..................................................................................................................................10-8

Register Map...................................................................................................................................10-9

Document Revision History...................................................................................................................10-11

Optrex 16207 LCD Controller Core..................................................................11-1

Core Overview............................................................................................................................................11-1

Functional Description............................................................................................................................. 11-1

Software Programming Model.................................................................................................................11-2

HAL System Library Support.......................................................................................................11-2

Displaying Characters on the LCD..............................................................................................11-2

Software Files..................................................................................................................................11-3

Register Map...................................................................................................................................11-3

Interrupt Behavior.........................................................................................................................11-3

Document Revision History.....................................................................................................................11-4

PIO Core............................................................................................................12-1

Core Overview............................................................................................................................................12-1

Functional Description............................................................................................................................. 12-1

Data Input and Output................................................................................................................. 12-2

Edge Capture.................................................................................................................................. 12-2

IRQ Generation..............................................................................................................................12-2

Example Configurations...........................................................................................................................12-3

Avalon-MM Interface....................................................................................................................12-3

Configuration.............................................................................................................................................12-3

Basic Settings.................................................................................................................................. 12-3

Input Options.................................................................................................................................12-4

Simulation.......................................................................................................................................12-5

Software Programming Model.................................................................................................................12-5

Software Files..................................................................................................................................12-5

Register Map...................................................................................................................................12-5

TOC-5

Altera Corporation