VC707_DDR3_datasheet

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DDR3 SDRAM SODIMM

MT8JTF12864HZ – 1GB

MT8JTF25664HZ – 2GB

MT8JTF51264HZ – 4GB

Features

• DDR3 functionality and operations supported as

defined in the component data sheet

• 204-pin, small-outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC3-12800, PC3-10600,

PC3-8500, or PC3-6400

• 1GB (128 Meg x 64), 2GB (256 Meg x 64),

4GB (512 Meg x 64)

• V

= 1.5V ±0.075V

• V

DDSPD

= 3.0–3.6V

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Single-rank

• Serial presence-detect (SPD) EEPROM

• 8 internal device banks

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 204-Pin SODIMM (MO-268 R/C B)

Module height: 30mm (1.181in)

Options Marking

• Operating temperature

– Commercial (0°C ≤ T

≤ +70°C) None

• Package

– 204-pin DIMM (halogen-free) Z

• Frequency/CAS latency

– 1.25ns @ CL = 11 (DDR3-1600) -1G6

– 1.5ns @ CL = 9 (DDR3-1333) -1G4

– 1.87ns @ CL = 7 (DDR3-1066) -1G1

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) t

RCD

(ns)

(ns)CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125

-1G4 PC3-10600 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125

-1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625

-1G0 PC3-8500 – – – 1066 – 800 667 15 15 52.5

-80B PC3-6400 – – – – – 800 667 15 15 52.5

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM

Features

PDF: 09005aef8441a29e

jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 1GB 2GB 4GB

Refresh count 8K 8K 8K

Row address 16K A[13:0] 32K A[14:0] 64K A[15:0]

Device bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0]

Device configuration 1Gb (128 Meg x 8) 2Gb (256 Meg x 8) 4Gb (512 Meg x 8)

Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]

Module rank address 1 S0# 1 S0# 1 S0#

Table 3: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT41J128M8,

1Gb DDR3 SDRAM

Part Number

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-

RCD-

RP)

MT8JTF12864HZ-1G6__ 1GB 128 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8JTF12864HZ-1G4__ 1GB 128 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT8JTF12864HZ-1G1__ 1GB 128 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Table 4: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41J256M8,

2Gb DDR3 SDRAM

Part Number

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-

RCD-

RP)

MT8JTF25664HZ-1G6__ 2GB 256 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8JTF25664HZ-1G4__ 2GB 256 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT8JTF25664HZ-1G1__ 2GB 256 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Table 5: Part Numbers and Timing Parameters – 4GB Modules

Base device: MT41J512M8,

4Gb DDR3 SDRAM

Part Number

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-

RCD-

RP)

MT8JTF51264HZ-1G6__ 4GB 512 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8JTF51264HZ-1G4__ 4GB 512 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT8JTF51264HZ-1G1__ 4GB 512 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Notes:

1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT8JTF51264HZ-1G6E1.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM

Features

PDF: 09005aef8441a29e

jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 7: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

CKx,

CKx#

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input

(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I

C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I

C bus.

CBx I/O Check bits: Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQSx#

I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with

read data; input with write data; center-aligned with write data.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM

Pin Descriptions

PDF: 09005aef8441a29e

jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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