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Verilog HDL Coding
Semiconductor Reuse Standard
IPMXDSRSHDL0001
SRS V3.2

SRS V3.2 01 FEB 20052
© Freescale Semiconductor, Inc. 2005
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any
claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale
was negligent regarding the design or manufacture of the part. Freescale and and the stylized Freescale logo are registered
trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. is an Equal Opportunity/Affirmative Action Employer.
Freescale Semiconductor
Revision History
Version Number Date Author Summary of Changes
1.0 29 JAN 1999 SoCDT Original
1.1 08 MAR 1999 SoCDT
Revision based on SRS development process.
Detailed history contained in DWG records.
2.0 06 DEC 1999 SoCDT
Revision based on SRS development process.
Detailed history contained in DWG records.
3.0 30 APR 2001
SoC-IP
Design Systems
Change summary location:
http://socdt.sps.mot.com/ddts/ddts_main
3.0.1 01 DEC 2001 SoC&IP Edit
3.0.2 15 MAR 2002 SoC&IP
Changed from MCP to MIUO; Changed
Motorola font batwing to batwing gif.
3.1 1 NOV 2002 SoC&IP Changed to reflect changes to SRS V3.1.
3.1.1 1 APR 2003 SoC&IP
Changed to reflect changes to SRS V3.1.1;
added eight new paragraph tags
3.2 01 FEB 2005 DEO Added updates for SRS V3.2.

SRS V3.2 01 FEB 2005 3
Semiconductor Reuse Standard
Freescale Semiconductor
Table of Contents
Section 7 Verilog HDL Coding
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
7.1.1 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
7.2 Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7.2.1 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7.2.2 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7.3 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7.3.1 File Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7.3.2 Naming of HDL Code Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7.4 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.4.1 File Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.4.2 Additional Construct Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.4.3 Other Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7.5 Code Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.6 Module Partitioning and Reusability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.7 Modeling Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.8 General Coding Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7.9 Standards for Structured Test Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.10 General Standards for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

SRS V3.2 01 FEB 20054
Semiconductor Reuse Standard
Freescale Semiconductor

SRS V3.2 01 FEB 2005 5
Semiconductor Reuse Standard
Freescale Semiconductor
List of Figures
Figure 7-1 Verilog File Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 7-2 Verilog Functions, User-Defined Primitives and Tasks Header. . . . . . . . . . . . . .21
Figure 7-3 Verilog Coding Format (Page 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 7-4 Verilog Coding Format (Page 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 7-5 Metastability Hazard Due to a Violation of this rule . . . . . . . . . . . . . . . . . . . . . . .29
Figure 7-6 Proper Use of Synchronization Register According to this rule. . . . . . . . . . . . . .29
Figure 7-7 Scan Support for Mixed Latch/Flip-Flop Designs . . . . . . . . . . . . . . . . . . . . . . . .38
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