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ZedBoard
(Zynq™ Evaluation and Development)
Hardware User’s Guide
Version 2.2
27 January 2014

Table of Contents
1 INTRODUCTION .................................................................................................................................. 2
1.1 ZYNQ BANK PIN ASSIGNMENTS ...................................................................................................... 4
2 FUNCTIONAL DESCRIPTION ............................................................................................................ 5
2.1 ALL PROGRAMMABLE SOC ............................................................................................................. 5
2.2 MEMORY ......................................................................................................................................... 5
2.2.1 DDR3 ...................................................................................................................................... 5
2.2.2 SPI Flash ................................................................................................................................ 7
2.2.3 SD Card Interface ..................................................................................................................10
2.3 USB ...............................................................................................................................................11
2.3.1 USB OTG ...............................................................................................................................11
2.3.2 USB-to-UART Bridge ............................................................................................................11
2.3.3 USB-JTAG .............................................................................................................................12
2.3.4 USB circuit protection ...........................................................................................................13
2.4 DISPLAY AND AUDIO ......................................................................................................................13
2.4.1 HDMI Output .........................................................................................................................13
2.4.2 VGA Connector......................................................................................................................16
2.4.3 I2S Audio Codec ....................................................................................................................17
2.4.4 OLED .....................................................................................................................................18
2.5 CLOCK SOURCES .............................................................................................................................18
2.6 RESET SOURCES .............................................................................................................................18
2.6.1 Power
‐
on Reset (PS_POR_B) ................................................................................................18
2.6.2 Program Push Button Switch .................................................................................................19
2.6.3 Processor Subsystem Reset ....................................................................................................19
2.7 USER I/O ........................................................................................................................................19
2.7.1 User Push Buttons .................................................................................................................19
2.7.2 User DIP Switches .................................................................................................................19
2.7.3 User LEDs .............................................................................................................................20
2.8 10/100/1000 ETHERNET PHY ........................................................................................................20
2.9 EXPANSION HEADERS ....................................................................................................................21
2.9.1 LPC FMC Connector .............................................................................................................21
2.9.2 Digilent Pmod™ Compatible Headers (2x6).........................................................................22
2.9.3 Agile Mixed Signaling (AMS) Connector, J2 .........................................................................23
2.10 CONFIGURATION MODES ................................................................................................................26
2.10.1 JTAG ......................................................................................................................................27
2.11 POWER ...........................................................................................................................................28
2.11.1 Primary Power Input .............................................................................................................28
2.11.2 On/Off Switch ........................................................................................................................28
2.11.3 Regulators ..............................................................................................................................28
2.11.4 Sequencing .............................................................................................................................29
2.11.5 Power Good LED ..................................................................................................................30
2.11.6 Power Estimation ..................................................................................................................30
2.11.7 Testing ...................................................................................................................................31
2.11.8 Probes ....................................................................................................................................31
3 ZYNQ-7000 AP SOC BANKS .............................................................................................................32
3.1 ZYNQ-7000 AP SOC BANK VOLTAGES ..........................................................................................33
4 JUMPER SETTINGS ............................................................................................................................34
5 MECHANICAL ....................................................................................................................................36
6 REVISION HISTORY ..........................................................................................................................37
27-Jan-2014
1

1 Introduction
The ZedBoard is an evaluation and development board based on the Xilinx Zynq
TM
-7000 All
Programmable SoC (AP SoC). Combining a dual Corex-A9 Processing System (PS) with 85,000
Series-7 Programmable Logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in
many applications. The ZedBoard’s robust mix of on-board peripherals and expansion
capabilities make it an ideal platform for both novice and experienced designers. The features
provided by the ZedBoard consist of:
• Xilinx® XC7Z020-1CLG484C Zynq-7000 AP SoC
o Primary configuration = QSPI Flash
o Auxiliary configuration options
Cascaded JTAG
SD Card
• Memory
o 512 MB DDR3 (128M x 32)
o 256 Mb QSPI Flash
• Interfaces
o USB-JTAG Programming using Digilent SMT1-equivalent circuit
Accesses PL JTAG
PS JTAG pins connected through PS Pmod
o 10/100/1G Ethernet
o USB OTG 2.0
o SD Card
o USB 2.0 FS USB-UART bridge
o Five Digilent Pmod™ compatible headers (2x6) (1 PS, 4 PL)
o One LPC FMC
o One AMS Header
o Two Reset Buttons (1 PS, 1 PL)
o Seven Push Buttons (2 PS, 5 PL)
o Eight dip/slide switches (PL)
o Nine User LEDs (1 PS, 8 PL)
o DONE LED (PL)
• On-board Oscillators
o 33.333 MHz (PS)
o 100 MHz (PL)
• Display/Audio
o HDMI Output
o VGA (12-bit Color)
o 128x32 OLED Display
o Audio Line-in, Line-out, headphone, microphone
• Power
o On/Off Switch
o 12V @ 5A AC/DC regulator
• Software
o ISE® WebPACK Design Software
o License voucher for ChipScope™ Pro locked to XC7Z020
27-Jan-2014
2

ZYNQ XC7
Z020-CLG484
DDR3
MIC In
Line In
Line Out
HdPhn Out
32
Pmods
QSPI
7
Pmod
Flash
8
14
Gbit
Enet
12
USB
OTG
8
SD
2
1 LED
,
2 buttons
USB
Cont
USB
UART
3
71
4
USB
Cont
Clk
FMC-LPC
GPIO (8 LEDs,
8
slide switches
,
5 pushbuttons)
Type A
HDMI Out
82
21
8
27
10
5
VGA (12-
bit color)
128x32 OLED
PHY
1
1
33Mhz
Reset
Primary JTAG
512Mbyte
DDR3 (
x32)
Multiplexed I/O (MIO)Processing System (PS)
Programmable Logic (PL)
1
PROG
Display
DDR
PS_RST
JTAG
PS_CLK
<User
Select>
ENET/
MDIO
USBOTG
SD
USBUART
PS_GPIO
QSPI
I2
S
/ACD
GPIO
FMC
PMOD
HDMI
VGA
OLED
PROG
PHY
HDMI
transmitter
I
2S Audio
Codec
XADC
8
GPIO/VP/VN
1
DONE LEDDONE
Clk
100Mhz
1
GCLK
Figure 1 – ZedBoard Block Diagram
27-Jan-2014
3

1.1 Zynq Bank Pin Assignments
The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table
that shows the detailed I/O connections.
Figure 2 - Zynq Z7020 CLG484 Bank Assignments
27-Jan-2014
4
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