MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 5
6.7 Frequency-modulated phase-locked loop (FMPLL) .....................................................................115
6.7.1 Introduction ..................................................................................................................115
6.7.2 Overview ......................................................................................................................115
6.7.3 Features .........................................................................................................................115
6.7.4 Memory map ................................................................................................................116
6.7.5 Register description ......................................................................................................116
6.7.6 Functional description ..................................................................................................120
6.7.7 Recommendations ........................................................................................................122
6.8 Clock monitor unit (CMU) ............................................................................................................123
6.8.1 Introduction ..................................................................................................................123
6.8.2 Main features ................................................................................................................123
6.8.3 Block diagram ..............................................................................................................124
6.8.4 Functional description ..................................................................................................124
6.8.5 Memory map and register description ..........................................................................126
Chapter 7
Clock Generation Module (MC_CGM)
7.1 Overview .......................................................................................................................................131
7.2 Features .........................................................................................................................................132
7.3 Modes of operation ........................................................................................................................133
7.3.1 Normal and reset modes of operation ...........................................................................133
7.4 External signal description ............................................................................................................133
7.5 Memory map and register definition .............................................................................................133
7.5.1 Register descriptions ....................................................................................................137
7.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................138
7.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................139
7.6 Functional Description ..................................................................................................................142
7.6.1 System Clock Generation .............................................................................................142
7.6.2 Output Clock Multiplexing ...........................................................................................143
7.6.3 Output Clock Division Selection ..................................................................................144
Chapter 8
Mode Entry Module (MC_ME)
8.1 Overview .......................................................................................................................................145
8.1.1 Features .........................................................................................................................145
8.1.2 Modes of operation .......................................................................................................146
8.2 External signal description ............................................................................................................147
8.3 Memory map and register definition .............................................................................................147
8.3.1 Register descriptions ....................................................................................................150
8.4 Functional description ...................................................................................................................163
8.4.1 Mode transition request ................................................................................................163
8.4.2 Modes details ................................................................................................................164
8.4.3 Mode transition process ................................................................................................167
8.4.4 Protection of mode configuration registers ..................................................................175
8.4.5 Mode transition interrupts ............................................................................................175
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