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LPDDR3 JEDEC官方specification; This document defines the LPDDR3 specification, including features, functionalities, ACand DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This specification was created using aspects of the following specifications: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Each aspect of the specification was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR3 specification.
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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD209-3
MAY 2012
JEDEC
STANDARD
Low Power Double Data Rate 3
(LPDDR3)
SPECIAL DISCLAIMER: JEDEC has received
information that certain patents or patent applications
may be essential to this standard. However, as of the
publication date of this standard, no statements
regarding an assurance or refusal to license such
patents or patent applications have been provided.
Contact JEDEC for further information.
JEDEC does not make any determination as to the
validity or relevancy of such patents or patent
applications. Anyone making use of the standard
assumes all liability resulting from such use. JEDEC
disclaims any representation or warranty, express or
implied, relating to the standard and its use.

NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and approved
through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal
counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the
proper product for use by those other than JEDEC members, whether the standard is to be used either
domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption may
involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to
any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or
publications.
The information included in JEDEC standards and publications represents a sound approach to product
specification and application, principally from the solid state device manufacturer viewpoint. Within the
JEDEC organization there are procedures whereby a JEDEC standard or publication may be further
processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in the
standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should
be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org
Published by
©JEDEC Solid State Technology Association 2012
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
PRICE: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved

PLEASE!
DON'T VIOLATE
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LAW!
This document is copyrighted by the JEDEC Solid State Technology
Association and may not be
reproduced without permission.
For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street, Suite 240 South
Arlington, Virginia 22201-2107
or call (703) 907-7559
or refer to www.jedec.org under Standards-Documents/Copyright Information

Special Disclaimer
JEDEC has received information that certain patents or patent applications
may be essential to this standard. However, as of the publication date of
this standard, no statements regarding an assurance or refusal to license
such patents or patent applications have been provided. Contact JEDEC
for further information.
JEDEC does not make any determination as to the validity or relevancy of
such patents or patent applications. Anyone making use of the standard
assumes all liability resulting from such use. JEDEC disclaims any
representation or warranty, express or implied, relating to the standard and
its use.

JEDEC Standard No. 209-3
Page 1
LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)
(From JEDEC Board ballot JCB-
-, formulated under the cognizance of the JC-42.6 Subcommittee on Low
Po
wer Memory.)
1Scope
This document defines the LPDDR3 specification, including features, functionalities, ACand DC characteristics,
packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements
for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This specification was created using
aspects of the following specifications: DDR2 (JESD79
-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2
(JESD209-2). Each aspect of the specification was considered and approved by committee ballot(s). The
accumulation of these ballots was then incorporated to prepare the LPDDR3 specification.
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