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Zynq-7000

All Programmable SoC

PCB Design Guide

UG933 (v1.12) September 27, 2016

Zynq-7000 PCB Design Guide www.xilinx.com 2

UG933 (v1.12) September 27, 2016

Revision History

The following table shows the revision history for this document.

Date Version Revision

06/04/2012 1.0

Initial Xilinx release.

06/06/2012 1.1

Corrected format issue.

08/29/2012 1.2

Updated Table 3-1 and Table 3-2 for additional devices/packages. Added 680 µF

capacitor specification to Table 3-3.

10/11/2012 1.2.1

Corrected document number (changed UG993 to UG933).

11/05/2012 1.2.2

Corrected sizing problem in PDF (no content change).

02/12/2013 1.3

Added Note

(2)

to Table 3-2. Added suggested part numbers to Table 3-3. Modified

paragraph under V

CCPAUX

– PS Auxiliary Logic Supply. Modified paragraph under

CCPLL

– PS PLL Supply. Added Figure 5-3. Modified second to last sentence and

added last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference

Voltage. Modified CAUTION! under Configuring the V

CCO_MIO0

, V

CCO_MIO1

Voltage

Mode and Note under DDR Supply Voltages. Changed Cke connection from a

pull-down resistor to a pull-up resistor in Figure 5-5 through Figure 5-7. Updated

entire MIO/EMIO IP Layout Guidelines section.

04/01/2013 1.4

Added XC7Z100 devices to Table 3-1 and Table 3-2. Updated ESR range values in

Table 3-3. Changed “0805 Ceramic Capacitor” section heading to Mid and High

Frequency Capacitors and modified first paragraph. Removed dimensions, changed

“0805” to “0402” in Figure 3-1 and deleted “0402 Ceramic Capacitor” subsection.

Deleted last sentence under , Modes and Attributes. Changed “minimum” to

“maximum” in third sentence of second paragraph under V

CCPLL

– PS PLL Supply.

Added second to last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR

Reference Voltage. Changed “Rup” to “Rterm” in Figure 5-5 and Figure 5-6. Deleted

Drst_b from Figure 5-6 and Figure 5-7. Changed Rup pull-up resistor to Rdown

pull-down resistor in Figure 5-7. Changed LPDDR2 setting in last row of Table 5-6 to

N/A. Updated values in first row of Table 5-9. Changed “Three” different topologies

to “two” under DDR Routing Topology. Removed Fly-by topology from Figure 5-8 and

Table 5-12. Deleted “NAND (ONFI),” “NOR/Flash/SRAM,” “SPI Master,” “SWDT (System

Watch Dog Timer),” and “TTC (Triple Time Counter” subsections from MIO/EMIO IP

Layout Guidelines and modified remaining subsections. Changed “EN208” to “EN247”

and “DS821” to “PG054” under Additional Resources and Legal Notices in Appendix B.

09/26/2013 1.5

Added XC7Z010, XC7Z015, and XC7Z030 packages/devices to Table 3-1 and Table 3-2.

Changed suggested part number for the 4.7 µF capacitor in Table 3-3. Added DDR ECC

unused pins to Table 5-5. Modified Figure 5-6 (Cke pins are now applied to GND via

resistor Rdown instead of VTT via Rterm). Expanded first paragraph under DDR

Termination. Clarified DDR Termination paragraph. Added fly-by routing to DDR

Routing Topology section. Deleted SD/SDIO Peripheral Controller section. Added last

sentence under sections IIC and SDIO and second sentence under QSPI. Added

Chapter 6, Migration from XC7Z030-SBG485/SBV485 to XC7Z015-CLG485 and

XC7Z012S-CLG485 Devices.

Send Feedback

Zynq-7000 PCB Design Guide www.xilinx.com 3

UG933 (v1.12) September 27, 2016

12/04/2013 1.6

Changed “DDR3” to “DDR3/3L” throughout document. Updated capacitor quantities

and packages in Table 3-1 and Table 3-2. Updated capacitor specifications in

Table 3-3. Updated descriptions for V

CCPINT

– PS Internal Logic Supply and V

CCPAUX

–

PS Auxiliary Logic Supply. Deleted “Capacitor Consolidation Rules” section. Modified

next-to-last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference

Voltage. Added paragraph preceding Table 5-5 and updated Table 5-5. Updated Addr,

Command, Contrl output name in Figure 5-7. Deleted last sentence under DDR Trace

Length.

08/01/2014 1.7

Removed “and Pin Planning Guide” from title. Added recommendation to

Recommended PCB Capacitors per Device. Changed V

CCO

per Bank sub-heading from

“100 µF” to 47 µF” in Table 3-1. Removed values for V

CCPLL

and replaced with

reference (Note 3) in Table 3-2. Changed “Terminal” type to “Terminal Tantalum” and

added “X7U” to 100 µF capacitor in Table 3-3. Modified first paragraph under Noise

Limits by removing specifications and adding a reference to the data sheet. Updated

second paragraph under Unconnected V

CCO

Pins. Changed Murata part number from

“GRM155R60J475ME47D” to “GRM155R60J474KE19” under Unconnected V

CCO

Pins.

Updated first paragraph under PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination

Voltage. Updated Unused DDR Memory. Deleted last two sentences under PS_POR_B

– Power on Reset and last sentence under PS_SRST_B – External System Reset.

Changed “Boot Mode Pins” section (pins MIO[2] to MIO[8] to Boot Mode Pins.

Modified Figure 5-5 (CKE resistor layout). Modified Figure 5-6 (changed clk signal to

differential signals CLK_P/CLK_N and added pull-down resistor to ODT). Added

separate column for DDR3L to Table 5-6 and modified values. Clarified DDR Trace

Length and DDR Trace Impedance sections. Clarified byte swapping under DDR

Routing Topology. Added last paragraph under Ethernet GEM. Deleted “Lower

Operating Frequencies (without Feedback Mode)” section from Chapter 6.

08/05/2014 1.7.1

Updated document to latest user guide template.

11/07/2014 1.8

Added XC7Z035 device to Table 3-1 and Table 3-2. Added 10 µF capacitor to Table 3-3.

Updated Table 5-5.

05/22/2015 1.9

Added Note under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference Voltage.

Added Caution following Table 5-3. Clarified Boot Mode Pins (changed first instance

of MIO[8] to MIO[8:2]. Updated Table 5-8. Clarified paragraph following Table 5-9.

Deleted last sentence under IIC. Clarified first paragraph under SDIO and second

sentence under UART. Deleted the word “maximum” preceding “hold time” in the

Important notice under QSPI.

09/25/2015 1.10

Added packages SBV485, FBV484, FBV676, and FFV676 to device XC7Z030, packages

FBV676, FFV676 and FFV900 to device XC7Z035, packages FBV676, FFV676, RFG676,

and FFV900 to device Z-7045, and packages FFV900, RF900, FFV1156, and RF1156 to

device XC7Z100 in Table 3-2. Added Bulk Capacitor Consolidation Rules in Chapter 3.

Deleted caution preceding Table 5-3. Updated requirements for PS_POR_B – Power on

Reset in Chapter 5. Updated DDR Routing Topology in Chapter 5. Added package

SBV485 to device Z-7100 in Differences between XC7Z030-SBG485/SBV485,

XC7Z015-CLG485, and XC7Z012S-CLG485 Devices in Chapter 6. Added Appendix A,

Processing System Memory Derating Tables.

03/31/2016 1.11

Added recommendations to IIC and SDIO in Chapter 5.

09/27/2016 1.12

Added single core devices XC7Z007S, XC7Z012S, and XC7Z014S to Table 3-1,

Table 3-2, and throughout text. Added migration information from XC7Z030-SBG485

to XC7012S-CLG485 devices in Chapter 6, updated Table 6-1, and added Processor

Differences in Chapter 6.

Date Version Revision

Send Feedback

Zynq-7000 PCB Design Guide www.xilinx.com 4

UG933 (v1.12) September 27, 2016

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Introduction

About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: PCB Technology Basics

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PCB Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Return Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 3: Power Distribution System

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCB Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Basic PDS Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Simulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PDS Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 4: SelectIO Signaling

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interface Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Single-Ended Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 5: Processing System (PS) Power and Signaling

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PS Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Boot Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Dynamic Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

MIO/EMIO IP Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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