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P1020 QorIQ Integrated Processor

Reference Manual

Supports: P1020 and P1011

Document Number: P1020RM

Rev. 6, 01/2013

Contents

Section number Title Page

Chapter 1

Overview

1.1 Overview.......................................................................................................................................................................61

1.1.1 Block diagram............................................................................................................................................61

1.1.2 Critical performance parameters................................................................................................................62

1.1.3 Chip-level features.....................................................................................................................................62

1.2 P1020 Application examples........................................................................................................................................64

1.2.1 Dual-core device application.....................................................................................................................64

1.2.2 High-performance communication system ...............................................................................................65

1.2.3 RAID controller application ......................................................................................................................66

1.2.4 SMB gateway application .........................................................................................................................67

1.2.5 WLAN access point application ...............................................................................................................68

1.3 Architecture overview...................................................................................................................................................69

1.3.1 e500v2 cores and memory unit..................................................................................................................69

1.3.2 e500 coherency module (ECM) and address map.....................................................................................70

1.3.3 Integrated security engine (SEC 3.3.2)......................................................................................................70

1.3.4 Enhanced three-speed Ethernet controllers................................................................................................71

1.3.5 Universal serial bus (USB) 2.0 controllers................................................................................................72

1.3.6 Enhanced secure digital host controller.....................................................................................................73

1.3.7 Serial peripheral interface (SPI).................................................................................................................73

1.3.8 DDR SDRAM controller...........................................................................................................................74

1.3.9 High-speed I/O interfaces..........................................................................................................................74

1.3.9.1 PCI Express interfaces...........................................................................................................75

1.3.9.2 SGMII....................................................................................................................................75

1.3.9.3 High-speed interface multiplexing.........................................................................................75

1.3.10 Programmable interrupt controller (PIC)...................................................................................................76

1.3.11 Time division multiplexing (TDM) interface ...........................................................................................76

P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013

Freescale Semiconductor, Inc. 3

Section number Title Page

1.3.12 DMA, I2C, DUART, and enhanced local bus controller...........................................................................76

1.3.13 Device boot locations.................................................................................................................................77

1.3.14 Boot sequencer...........................................................................................................................................77

1.3.15 System performance monitor.....................................................................................................................78

Chapter 2

Memory Map

2.1 Overview.......................................................................................................................................................................79

2.2 Configuration, control, and status registers..................................................................................................................80

2.2.1 Accessing CCSR memory from the local processor..................................................................................81

2.2.2 Accessing CCSR memory from external masters......................................................................................81

2.2.3 Organization of CCSR space.....................................................................................................................82

2.2.3.1 General utilities registers.......................................................................................................82

2.2.3.1.1 General utilities register organization.............................................................83

2.2.3.2 Programmable interrupt controller registers..........................................................................84

2.2.4 Device-specific utilities registers...............................................................................................................85

2.2.5 CCSR address map.....................................................................................................................................86

2.3 Local access windows...................................................................................................................................................88

2.3.1 Precedence of local access windows .........................................................................................................89

2.3.2 Configuring local access windows.............................................................................................................89

2.3.3 Distinguishing local access windows from other mapping functions........................................................90

2.3.4 Illegal interaction between local access windows and DDR chip selects..................................................90

2.3.5 Local address map example.......................................................................................................................90

2.4 Local Access Window Registers..................................................................................................................................91

2.4.1 Local access window n base address register (LAW_LAWBARn)..........................................................93

2.4.2 Local access window n attribute register (LAW_LAWARn)....................................................................93

2.5 Address translation and mapping units.........................................................................................................................95

2.5.1 Address translation ....................................................................................................................................95

2.5.2 Outbound ATMUs.....................................................................................................................................96

P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013

4 Freescale Semiconductor, Inc.

Section number Title Page

2.5.3 Inbound ATMUs........................................................................................................................................96

2.5.3.1 Illegal interaction between inbound ATMUs and LAWs......................................................97

Chapter 3

Signal Descriptions

3.1 General overview..........................................................................................................................................................99

3.2 Signals overview...........................................................................................................................................................99

3.3 Configuration signals sampled at reset.........................................................................................................................109

3.4 Output Signal States During Reset...............................................................................................................................111

Chapter 4

Reset, Clocking, and Initialization

4.1 Overview.......................................................................................................................................................................115

4.2 Reset external signal descriptions.................................................................................................................................115

4.2.1 System control signals...............................................................................................................................116

4.2.2 Clock signals..............................................................................................................................................117

4.3 Accessing configuration, control, and status registers..................................................................................................118

4.3.1 Updating CCSRBAR.................................................................................................................................118

4.3.2 Accessing alternate configuration space....................................................................................................119

4.3.3 Boot page translation.................................................................................................................................120

4.3.4 Boot sequencer...........................................................................................................................................120

4.4 Reset Memory Map/Register Definition.......................................................................................................................120

4.4.1 Configuration, control, and status registers base address register (reset_CCSRBAR)..............................121

4.4.2 Alternate configuration base address register (reset_ALTCBAR)............................................................122

4.4.3 Alternate configuration attribute register (reset_ALTCAR)......................................................................122

4.4.4 Boot page translation register (reset_BPTR).............................................................................................123

4.5 Functional description...................................................................................................................................................123

4.5.1 Reset operations.........................................................................................................................................123

4.5.1.1 Soft reset................................................................................................................................124

4.5.1.2 Hard reset...............................................................................................................................124

4.5.2 Power-on reset sequence............................................................................................................................124

P1020 QorIQ Integrated Processor Reference Manual, Rev. 6, 01/2013

Freescale Semiconductor, Inc. 5