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首页基于Xilinx平台的嵌入式软件开发流程
基于Xilinx平台的嵌入式软件开发流程 在过去的Linux内核源码中,存在大量对板级细节信息描述的代码。这些代码充斥在/arch/arm/plat-xxx和/arch/arm/mach-xxx目录,对内核而言这些 platform设备、resource、i2c_board_info、spi_board_info以及各种硬件的platform_data绝大多数纯属垃圾冗余代码 为了解决这一问题,ARM内核版本3.x之后引入了原先在Power PC等其他体系架构已经使用的Flattened Device Tree。Device Tree改变了原来用 hardcode方式将HW 配置信息嵌入到内核代码的方法,改用bootloader传递一个DataBase的形式。 对于基于ARM CPU的嵌入式系统,我们习惯于针对每一个platform进行内核的编译。但是随着ARM在消费类电子上的广泛应用(甚至桌面系统、服务器系 统),我们期望ARM能够象X86那样用一个kernel image来支持多个platform。 在这种情况下,如果我们认为kernel是一个black box,那么其输入参数应该包括: 识别platform的信息 runtime的配置参数 设备的拓扑结构以及特性 对于嵌入式系统,在系统启动阶段,bootloader会加载内核并将控制权转交给内核,此外,还需要把上述的三个参数信息传递给kernel,以便kernel可以有 较大的灵活性。在linux kernel中,Device Tree的设计目标就是如此
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1Resource
U-boot
U-Boot source code
https://github.com/Xilinx/u-boot-xlnx
device tree compiler
device tree generator for Xilinx SDK
https://github.com/Xilinx/device-tree-xlnx
Linux OS
Xilinx Open Source Linux: PetaLinux
http://www.xilinx.com/petalinux
Embedded Design Hub - PetaLinux
http://www.xilinx.com/support/documentation-navigation/design-hubs/dh0016-petalinux-tools-hub.html
from ADI
https://github.com/analogdevicesinc/linux
Third-party OS
http://www.wiki.xilinx.com/3rd+Party+Operating+Systems
Real-Time Linux
http://www.wiki.xilinx.com/Real-Time+Linux
Ubuntu on Zynq
http://www.wiki.xilinx.com/Ubuntu+on+Zynq
Yocto Open Linux project
http://www.wiki.xilinx.com/Yocto
http://git.yoctoproject.org/cgit/cgit.cgi/meta-xilinx/
Drivers & Libraries
Linux Drivers:
http://www.wiki.xilinx.com/Linux+Drivers
Bare-metal Drivers and Libraries
http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries
Documents
The Xilinx Design Flow:Getting Started
http://www.wiki.xilinx.com/Getting+Started
Technical Articles
http://www.wiki.xilinx.com/Technical+Articles
Zynq Linux
http://www.wiki.xilinx.com/Zynq+Linux
SDK software development online documents
https://www.xilinx.com/html_docs/xilinx2017_4/SDK_Doc/index.html
2Keywordsandrelatedinformatioin
Bootloader
u-boot
make and build
Linux Kernel
File system
root file system
standard desktop OS
file system mount
Device
driver
device tree compiler and blobber
insmod
Firmware
Library and Middleware
static library
dynamic library
cross compile/debug
Debug
PL simulation and debug
Software debug
PS-PL co-debug, co-simulation
IDE and related build tools
Eclipse-likeVivado SDK
Petalinux
Profiling
3TopLevelOverviewofXilinxdesignlowforZynqSOC

注意不同颜色代表的不同片内互联:
AXI-3 32bits/64bits:AXI4-HP
AXI 64bits:Intra Processor System High-speed Interconnect (among DRAM, Central Inteconnect, Master IOP, AXI-GP Master, AXI-GP
Slave, OCM
AXI 32bits: AXI-GP Master/Slave and L2 Cache
AHB 32bits: from High Speech IO Peripherals (USB, Ethernet and SDIO) to IOP Master
APB 32bits: from IOP Slave to Low Speed IOP (UART, I2C, SPI, CAN and GPIO)

3 different design flows which you need to know
-------------------------------------------------------------------------------------------------------
A System design & Hardware design
Tools: Vivado
What your are supposed to do:
Hardware configuration (PL and PS)
Input and Output
Interface for PL and PS
clock frequency
PL-PS configuration
Debug
Boot device
Traditional FPGA development methodology
customized IP design
Xilinx IP intergration
RTL-based FPGA subsystem design, intergration, simulation, synthesis, implementation and debug

PL-PS co-design and co-debug
complex and is commonly system bottleneck, lots of debug, test tools and methods are designed around this domain
Delivery by vivado:
XML file: Programmable Logic (PL) informationdescribing processors, peripherals, memory maps, and additional system data
INIT files: (
.h
,
.c
, and
.tcl
files) used by software design tools to create and configure Board Support Package (
BSP
) libraries, infer
compiler options, define JTAG settings, and automate other operations that require information about the hardware.
bitstream
file:programmable logic (PL) bit file
BMM
file:A block RAM memory map (BMM) file
B System Software development
Tools: Vivado SDK
Create Boot Image
import hardware design files (HDF)
create and build FSBL
create and build U-boot
delivery: boot.bin
Build OS (here use Linux)
build Linux Kernel (delivery:uImage or zImage)
build Device Tree Blob (delivery:
devicetree.dtb
)
build root file system (delivery: rootfs, rootramfs
filesystem-1: build RamDisk Root File System (delivery:
uImage
or
zImage
)
filesystem-2: standard Linux File System (delivery:
extracted
ext3/4
partition, mount required)
C Application Software development
Tools:Vivado SDK/SDSOC
What to do:
traditional CPU-based only application software (drivers, libaries, middleware, lightweight OS or bare-metal, your applications)
software with CPU-FPGA co-design, commonly is kind of intensive and high-speed data flow and algorithm accerleration
Procedures
-------------------------------------------------------------------------------------------------------
Step 1:architecturedefinition and design of software-hardware system
hardware definition and setting (clock frequency, low-speed interface, high-speed interface, interrupt, GPIO etc.)
resource budget of FPGA
software processing budget
top-level timing and throughput
FPGA sub-system level timing and throughput
CPU software level throughput
function mapping/partition into software and hardware
Step 2:hardware configuration and FPGA subsystem design
design hardware system, including IP development, FPGA subsystem development and hardware part of PL-PS communication.
Step 3:handover fromhardware to SDK
hardware abstraction through compiling vivado hardware project and generating related HDF files. Since now, hardware part is done,
PL part is successfully abstracted as binary file and some configuration files
export to SDK environment then let's turn to focus on software part
Step 4:launch Vivado SDK and build the necessary system software environment
Here, you should need know which kind of software project you want to build
option-1: Bare-metal software application (with only necessary libraries and hardware driver and no OS), typically it is a kind of single-
thread unlimitted loop-based wait-activation-work-wait application
option-2: software project with light-weight OS (multiple tasks, GUI, more device drivers support etc.)
Step 5:build basic BSP software (for bare-metal applicaiton)
basic software functional libraries
hardware-level driver including PL
basic boot environment (except U-boot)
Step 6:build Linux OS environment (optional)
Step 7:develop application software
4.SystemSoftwaredevelopment

Procedures:
Step 1:Build FSBL (BSP)
Step 2:Build U-Boot and generate boot.bin (SSBL)
Step
3
:Build
Linux Kernel
Step
4
:Build
Device Tree Blob
Step 5:Build Root File System
Step 6:Prepare Boot Image and programm into boot device
Step 7:Setup serial-port console
Step 8:Power-on reset
devicetree forZynq:
-------------------------------------------------------------------------------------------------------------------------
device tree is a data structure of nodes and properties describing components and features supported by the hardware (PS peripherals,
ARM processors, and PL peripherals).
The nodes provide information such as the hardware-component map address, interrupt number, default settings, etc.
device tree information is passed to Linux kernel at boot time. While booting, the kernel uses this information to load the corresponding
device drivers
background information of device tree:
在过去的Linux内核源码中,存在大量对板级细节信息描述的代码。这些代码充斥在/arch/arm/plat-xxx和/arch/arm/mach-xxx目录,对内核而言这些
platform设备、resource、i2c_board_info、spi_board_info以及各种硬件的platform_data绝大多数纯属垃圾冗余代码
为了解决这一问题,ARM内核版本3.x之后引入了原先在Power PC等其他体系架构已经使用的Flattened Device Tree。Device Tree改变了原来用
hardcode方式将HW 配置信息嵌入到内核代码的方法,改用bootloader传递一个DataBase的形式。
对于基于ARM CPU的嵌入式系统,我们习惯于针对每一个platform进行内核的编译。但是随着ARM在消费类电子上的广泛应用(甚至桌面系统、服务器系
统),我们期望ARM能够象X86那样用一个kernel image来支持多个platform。
在这种情况下,如果我们认为kernel是一个black box,那么其输入参数应该包括:
识别platform的信息
runtime的配置参数
设备的拓扑结构以及特性
对于嵌入式系统,在系统启动阶段,bootloader会加载内核并将控制权转交给内核,此外,还需要把上述的三个参数信息传递给kernel,以便kernel可以有
较大的灵活性。在linux kernel中,Device Tree的设计目标就是如此。
Device Tree的描述信息
CPU的数量和类别
内存基地址和大小
总线和桥
外设连接
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