4
Introduction ..........................................................................7
High-Speed Interface Technologies Overview..............9
1.1 Differential Signaling Technology ....................................... 9
1.2 LVDS – Low-Voltage Differential Signaling .....................10
1.3 CML – Current-Mode Logic .................................................11
1.4 Low-Voltage Positive-Emitter-Coupled Logic .................12
1.5 Selecting An Optimal Technology .....................................12
Network Topology .............................................................15
2.1 Point-to-Point ........................................................................15
2.2 Multipoint / Multidrop ..........................................................16
2.3 SerDes Architectures ...........................................................17
2.4 Mixing Signaling Technologies ......................................... 17
2.5 Selecting an Interface Technology ...................................17
SerDes Architectures .......................................................19
3.1 Introduction ............................................................................19
3.2 Parallel Clock SerDes ..........................................................19
3.3 Embedded Clock (Start-Stop) Bits SerDes .......................20
3.4 8b/10b SerDes ........................................................................ 21
3.5 FPGA-Attach SerDes ............................................................22
3.6 Applications ...........................................................................23
Parallel Clock SerDes ....................................................23
Embedded Clock (Start-Stop) Bits SerDes .................24
8b/10b SerDes .................................................................. 26
FPGA-Attach SerDes ...................................................... 27
3.7 Comparison Overview ..........................................................28
3.8 Summary ................................................................................. 29
Termination and Translation ............................................31
4.1 Terminations and Impedance Matching ........................... 31
4.2 Multidrop and Multipoint .................................................... 31
4.3 AC Coupling ...........................................................................32
4.4 DC Balance ............................................................................33
Selecting a Capacitor ..................................................... 34
4.5 Translation .............................................................................35
4.6 Failsafes .................................................................................37
M-LVDS Failsafes ............................................................ 38
Design and Layout Guidelines ........................................39
5.1 PCB Transmission Lines ...................................................... 39
5.2 Transmission Loss ................................................................40
5.3 PCB Vias ................................................................................. 41
5.4 Backplane Subsystem .........................................................42
5.5 Decoupling ............................................................................. 44
Jitter Overview ..................................................................47
6.1 Introduction ............................................................................47
Random Jitter Characteristics ......................................47
Deterministic Jitter ......................................................... 48
Duty Cycle Distortion ...................................................... 49
Inter-Symbol Interference .............................................50
Periodic Jitter ..................................................................52
6.2 Additional Jitter Sources .................................................... 52
Effect of Input Capacitance ...........................................53
FEXT/NEXT ........................................................................53
Systems Susceptible to Crosstalk ...............................54
Bit Error Rate .................................................................... 54
6.3 Pattern Dependencies and Eye Diagrams ........................ 55
Eye Masks ........................................................................ 57
Bathtub Curves and Eye Contours ................................57
Interconnect Media and Signal Conditioning ..............59
7.1 Physical and Electrical Cable Characteristics ............... 59
7.2 Signal-Conditioning Characteristics ................................ 63
Media Losses in Cables and PCB Traces ................... 63
Pre-Emphasis and De-Emphasis Drivers ....................64
Equalization ...................................................................... 65
Two Types of Equalizer Circuits ................................... 66
Passive: Power-Saver Equalizers ................................ 66
Active Equalizers ............................................................ 66
Fixed Equalizers .............................................................. 67
Variable Equalizers Allow Control ............................... 67
Adaptive Equalizers ........................................................67
Crosstalk ...........................................................................68
Reflections ........................................................................ 68
Contents
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