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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

AWR1642

SWRS203A –MAY 2017–REVISED APRIL 2018

AWR1642 Single-Chip 77- and 79-GHz FMCW Radar Sensor

1 Device Overview

1.1 Features

• FMCW Transceiver

– Integrated PLL, Transmitter, Receiver,

Baseband, and A2D

– 76- to 81-GHz Coverage With 4 GHz Available

Bandwidth

– Four Receive Channels

– Two Transmit Channels

– Three Transmit Channels

– Ultra-Accurate Chirp (Timing) Engine Based on

Fractional-N PLL

– TX Power: 12.5 dBm

– RX Noise Figure:

– 14 dB (76 to 77 GHz)

– 15 dB (77 to 81 GHz)

– Phase Noise at 1 MHz:

– –95 dBc/Hz (76 to 77 GHz)

– –93 dBc/Hz (77 to 81 GHz)

• Built-in Calibration and Self-Test (Monitoring)

– ARM

Cortex

-R4F-Based Radio Control

System

– Built-in Firmware (ROM)

– Self-calibrating System Across Frequency and

Temperature

• C674x DSP for FMCW Signal Processing

• On-Chip Memory: 1.5MB

• Cortex-R4F Microcontroller for Object Tracking and

Classification, AUTOSAR, and Interface Control

– Supports Autonomous Mode (Loading User

Application from QSPI Flash Memory)

• Integrated Peripherals

– Internal Memories With ECC

• Host Interface

– CAN (Two Instances, One Being CAN-FD)

• Other Interfaces Available to User Application

– Up to 6 ADC Channels

– Up to 2 SPI Channels

– Up to 2 UARTs

– I

– GPIOs

– 2-Lane LVDS Interface for Raw ADC Data and

Debug Instrumentation

• ASIL B Targeted

• AECQ100 Qualified

• AWR1642 Advanced Features

– Embedded Self-monitoring With No Host

Processor Involvement

– Complex Baseband Architecture

– Embedded Interference Detection Capability

• Power Management

– Built-in LDO Network for Enhanced PSRR

– I/Os Support Dual Voltage 3.3 V/1.8 V

• Clock Source

– Supports External Oscillator at 40 MHz

– Supports Externally Driven Clock (Square/Sine)

at 40 MHz

– Supports 40 MHz Crystal Connection with Load

Capacitors

• Easy Hardware Design

– 0.65-mm Pitch, 161-Pin 10.4 mm × 10.4 mm

Flip Chip BGA Package for Easy Assembly and

Low-Cost PCB Design

– Small Solution Size

• Supports Automotive Temperature Operating

Range

1.2 Applications

• Blind Spot Detection

• Lane Change Assistance

• Cross Traffic Alert

• Parking Assistance

• Occupancy Detection

• Simple Gesture Recognition

• Car Door Opener Applications

AWR1642

SWRS203A –MAY 2017–REVISED APRIL 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: AWR1642

Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 7

3.1 Related Products ..................................... 8

4 Terminal Configuration and Functions.............. 9

4.1 Pin Diagram .......................................... 9

4.2 Pin Attributes ........................................ 13

4.3 Signal Descriptions.................................. 24

5 Specifications........................................... 29

5.1 Absolute Maximum Ratings ......................... 29

5.2 ESD Ratings ........................................ 29

5.3 Power-On Hours (POH)............................. 29

5.4 Recommended Operating Conditions............... 30

5.5 Power Supply Specifications........................ 30

5.6 Power Consumption Summary...................... 31

5.7 RF Specification..................................... 32

5.8 CPU Specifications.................................. 33

5.9 Thermal Resistance Characteristics for FCBGA

Package [ABL0161] ................................. 33

5.10 Timing and Switching Characteristics ............... 34

6 Detailed Description ................................... 58

6.1 Overview ............................................ 58

6.2 Functional Block Diagram........................... 58

6.3 Subsystems ......................................... 58

6.4 Other Subsystems................................... 65

7 Monitoring and Diagnostics.......................... 67

7.1 Monitoring and Diagnostic Mechanisms ............ 67

8 Applications, Implementation, and Layout........ 72

8.1 Application Information.............................. 72

8.2 Short-Range Radar ................................. 72

8.3 Reference Schematic ............................... 72

8.4 Layout ............................................... 75

9 Device and Documentation Support ............... 79

9.1 Device Nomenclature ............................... 79

9.2 Tools and Software ................................. 80

9.3 Documentation Support ............................. 80

9.4 Community Resources .............................. 81

9.5 Trademarks.......................................... 81

9.6 Electrostatic Discharge Caution..................... 81

9.7 Export Control Notice ............................... 81

9.8 Glossary............................................. 81

10 Mechanical, Packaging, and Orderable

Information .............................................. 82

10.1 Packaging Information .............................. 82

AWR1642

www.ti.com

SWRS203A –MAY 2017–REVISED APRIL 2018

Submit Documentation Feedback

Product Folder Links: AWR1642

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from May 1, 2017 to April 30, 2018 (from * Revision (May 2017) to A Revision) Page

• Updated/Changed document from ADVANCE INFORMATION to PRODUCTION DATA .................................. 1

• Updated/Changed TX Power from "12 dBm" to "12.5 dBm" .................................................................... 1

• Updated/Changed RX Noise Figure from "15 dB (76 to 77 GHz)" to "14 dB (76 to 77 GHz)" ............................. 1

• Updated/Changed RX Noise Figure from "16 dB (77 to 81 GHz)" to "15 dB (77 to 81 GHz)" ............................. 1

• Updated/Changed Phase Noise at 1 MHz from " –94 dBc/Hz (76 to 77 GHz)" to " –95 dBc/Hz (76 to 77 GHz)"....... 1

• Updated/Changed Phase Noise at 1 MHz from "–91 dBc/Hz (77 to 81 GHz)" to "–93 dBc/Hz (77 to 81 GHz)" ........ 1

• Updated/Changed Features from "ASIL B Capable" to "ASIL B Targeted"................................................... 1

• Removed "40.0 MHz Crystal With Internal Oscillator" bullet.................................................................... 1

• Updated/Changed Features from "External Oscillator at 40 and 50 MHz" to "External Oscillator at 40 MHz"........... 1

• Updated/Changed Features from "...Driven Clock (Square/Sine) at 40 and 50 MHz" to "...Driven Clock

(Square/Sine) at 40 MHz" ........................................................................................................... 1

• Added "Supports 40 MHz Crystal Connection..."................................................................................. 1

• Updated RX and TX connections in Functional Block Diagram ................................................................ 3

• Added GPADC block to Functional Block Diagram .............................................................................. 3

• Updated/Changed Functional Block Diagram footnote text from "576 KB to 512 KB" ...................................... 3

• Added AWR1243P to Device Features Comparison............................................................................. 7

• Updated/Changed Device Features Comparison ASIL for AWR1243P, AWR1243, and AWR1642 from "B-

Capable" to "B-Targeted" ............................................................................................................ 7

• Added "Max complex sampling rate (Msps)" to Device Features Comparison............................................... 7

• Corrected A10 pin to "VOUT_14APLL"........................................................................................... 10

• Updated Top Right Quadrant image to match complete Pin Diagram ....................................................... 12

• Updated/Changed N14 from GPIO48 to DMM_SYNC ......................................................................... 16

• Added two register tables after Pin Attributes ................................................................................... 21

• Updated/Changed PAD IO Control Registers ................................................................................... 21

• Updated/Changed CLKP and CLKM descriptions in Signal Descriptions ................................................... 27

• Removed R14 from Power supply VIOIN ........................................................................................ 27

• Added pin R15 to Power supply VSS ............................................................................................ 28

• Added footnote to V

(ESD)

............................................................................................................ 29

• Updated/Changed V

in Recommended Operating Conditions............................................................... 30

• Updated/Changed V

MIN from "85% VIOIN" to "VIOIN – 450"............................................................. 30

• Deleted CLKP and CLKM row in Recommended Operating Conditions..................................................... 30

• Updated/Changed V

MAX from "350" to "450" ............................................................................... 30

• Added NRESET row to Recommended Operating Conditions................................................................ 30

• Completely updated Ripple Specifications table ................................................................................ 31

• Updated/Changed Current consumption from "Total current drawn by all nodes driven by 1.3V rail" to "Total

current drawn by all nodes driven by 1.3V or 1.0V raisl" ...................................................................... 31

• Updated Average Power Consumption at Power Terminals .................................................................. 31

• Added footnote to RF Specification .............................................................................................. 32

• Updated/Changed RF Specification Receiver from "...(Out of Band)..." to "...(Out of Band / Specified at 10 kHz)...". 32

• Updated/Changed RF Specification Receiver 1-dB compression Point from "–5 dBm" to "–8 dBm".................... 32

• Updated/Changed RF Specification Receiver from "IQ gain mismatch" to "Image Rejection Ratio (IMRR)" ........... 32

• Removed IQ phase mismatch from RF Specification .......................................................................... 32

• Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "A2D sampling rate

(complex 1x)" ........................................................................................................................ 32

• Added multiple row to RF Specification Receiver............................................................................... 32

• Updated/Changed Power Supply Sequencing and Reset Timing image .................................................... 34

• Updated/Changed Crystal Implementation image from "40 and 50 MHz" to "40 MHz".................................... 35

• Updated/Changed Crystal Implementation text from "XTALP" and "XTALM" to "CLKP" and "CLKM" .................. 35

• Updated Frequency tolerance from ±50 to ±200................................................................................ 35

• Added External Clock Electrical Characteristics ................................................................................ 36

• Added External Clock Mode Specifications...................................................................................... 36

• Updated SPI Slave Mode Switching Parameters ............................................................................... 42

• Updated SPI Slave Mode Timing Requirements................................................................................ 42

• Updated/Changed QSPI Timing Requirements t

su(D-SCLK)

MIN value from "6.3" to " 7.3" ................................... 52

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