ARMcortexM0M0+SDK参考系统

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ARM DUI 0559C (ID041913)

Cortex

™

-M0 and Cortex-M0+ System

Design Kit

Revision: r1p0

Example System Guide

Confidential

ID041913 Confidential

Cortex-M0 and Cortex-M0+ System Design Kit

Example System Guide

Release Information

The following changes have been made to this book.

Proprietary Notice

Words and logos marked with

™

are registered trademarks or trademarks of ARM

in the EU and other countries,

except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the

trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be

adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the

product and its use contained in this document are given by ARM in good faith. However, all warranties implied or

expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or

damage arising from the use of any information in this document, or any error or omission in such information, or any

incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Confidential. This document may only be used and distributed in accordance with the terms of the

agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

Change history

Date Issue Confidentiality Change

17 March 2011 A Non-Confidential First release for r0p0

15 June 2011 B Confidential Second release for r0p0

19 April 2013 C Confidential First release for r1p0

ID041913 Confidential

Contents

Cortex-M0 and Cortex-M0+ System Design Kit

Example System Guide

Preface

About this book ........................................................................................................... vi

Feedback .................................................................................................................... ix

Chapter 1 Introduction

1.1 About the Cortex-M0 and Cortex-M0+ System Design Kit ...................................... 1-2

1.2 Cortex-M0 and Cortex-M0+ System Design Kit directory structure ......................... 1-3

1.3 Limitations of the design kit ..................................................................................... 1-5

Chapter 2 Functional Description

2.1 System-level design and design hierarchy .............................................................. 2-2

2.2 Design files .............................................................................................................. 2-8

2.3 Processor file locations .......................................................................................... 2-10

2.4 Configuration options ............................................................................................. 2-11

2.5 Memory map .......................................................................................................... 2-16

2.6 System controller ................................................................................................... 2-19

2.7 I/O pins .................................................................................................................. 2-22

2.8 Interrupts and event functions ............................................................................... 2-24

2.9 AHB system ROM table ......................................................................................... 2-26

2.10 Clock and reset ...................................................................................................... 2-27

2.11 SysTick support ..................................................................................................... 2-28

2.12 Handling the Engineering Change Order (ECO) Revision Number in ID registers 2-29

Chapter 3 Example System Testbench

3.1 About the testbench design ..................................................................................... 3-2

3.2 UART text output capturing and escape code ......................................................... 3-3

ID041913 Confidential

3.3 Debug tester ............................................................................................................ 3-4

Chapter 4 Using the Simulation Environment

4.1 About the simulation environment ........................................................................... 4-2

4.2 Files and directory structure .................................................................................... 4-3

4.3 Setting up the simulation environment ..................................................................... 4-5

4.4 Running a simulation in the simulation environment ............................................... 4-8

Chapter 5 Software Examples

5.1 Available simulation tests ........................................................................................ 5-2

5.2 Creating a new test .................................................................................................. 5-5

5.3 Example header files and device driver files ........................................................... 5-6

5.4 Retargeting .............................................................................................................. 5-8

5.5 Example device driver software ............................................................................... 5-9

Chapter 6 Synthesis

6.1 Implementation overview ......................................................................................... 6-2

6.2 Directory structure and files ..................................................................................... 6-3

6.3 Implementation flow ................................................................................................. 6-4

6.4 Timing constraints .................................................................................................... 6-5

Appendix A Debug Tester

A.1 About the debug tester ............................................................................................ A-2

A.2 Memory map ............................................................................................................ A-3

A.3 Debug tester software .............................................................................................. A-4

Appendix B Revisions

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