UG586赛灵思DDR3的IP核（MIG）详细文档_ug586

DDR3

MIG

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7 Series FPGAs

Memory Interface

Solutions v1.7

User Guide

UG586 October 16, 2012

7 Series FPGAs Memory Interface Solutions www.xilinx.com UG586 October 16, 2012

Notice of Disclaimer

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Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product

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subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm

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owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision

03/01/11 1.0 Initial Xilinx release.

06/22/11 1.1 MIG 1.2 release. Updated ISE Design Suite version to 13.2. Updated GUI screen captures

throughout document.

Chapter 1: Added Verify Pin Changes and Update Design, Simulating the Example

Design (for Designs with the AXI4 Interface), Simulation Considerations, Error

Correcting Code, and DDR3 Pinout Examples sections. Added paragraph about SLRs to

Pin Compatible FPGAs, page 17. Added Input Clock Period and PHY to Controller

bullets in Controller Options, page 19. To Setting DDR3 Memory Parameter Option,

page 23, indicated that DDR3 SDRAM supports burst lengths of 8. Added Internal

Termination for High Range Banks option under Figure 1-17. Added bulleted item about

Pin/Bank selection mode on page 26. Added notes about chip select and data mask

options on page 50. Added app_correct_en_i to Table 1-17. Added three command types

to Command Path, page 103. Added phy_mc_ctl_full, phy_mc_cmd_full, and

phy_mc_data_full signals to Table 1-86. Added paragraph about FIFOs at the end of

Physical Layer Interface (Non-Memory Controller Design), page 131. Updated the

description and options for DATA_BUF_ADDR_WIDTH in Table 1-92. Added bullet

about SLRs to Bank and Pin Selection Guides for DDR3 Designs, page 144. Added

LVCMOS15 and DIFF_SSTL15 I/O standards to Configuration, page 146. Changed

resistor values in Figure 1-70, Figure 1-71, and Figure 1-72. Changed resistor values in

FPGA DCI or IN_TERM column in Table 1-95.

Chapter 2: Added the Verify Pin Changes and Update Design and Output Path sections.

Revised latency mode description on page 184. Added bulleted item about Pin/Bank

selection mode on page 189. Added Internal Termination for High Range Banks option

under Figure 2-16. Updated Implementation Details, page 215.

Chapter 3: Added new chapter on RLDRAM II.

UG586 October 16, 2012 www.xilinx.com 7 Series FPGAs Memory Interface Solutions

10/19/11 1.2 MIG 1.3 release. Updated ISE Design Suite version to 13.3.

• Chapter 1: Added step 2 to MIG Output Options, page 16. Added note about optional

use of the memory controller to Controller Options, page 19. Added arbitration

scheme to AXI Parameter Options, page 22. Added description of DCI Cascade under

Figure 1-17. Updated text about devices with SSI technology and SLRs on page 27 and

page 145. Changed error to tg_compare_error on page 29. Replaced Table 1-8. Added

qdr_wr_cmd_o, vio_fixed_instr_value, vio_fixed_bl_value, vio_pause_traffic, and

vio_data_mask_gen signals to Table 1-13. Added signals to the User Interface in

Figure 1-31 and Figure 1-33. Added app_sr_req, app_sr_active, app_ref_req,

app_ref_ack, app_zq_req, and app_zq_ack signals to Table 1-17. Added

app_wdf_rdy, app_ref_req, app_ref_ack, app_zq_req, app_zq_ack, Read Priority

with Starve Limit (RD_PRI_REG_STARVE_LIMIT), Native Interface Maintenance

Command Signals, User Refresh, and User ZQ sections. Added

C_RD_WR_ARB_ALGORITHM to Table 1-19. Updated fields in Table 1-84, changed

Hi Index (Rank) to Rank Count, and added CAS slot field. Updated AXI Addressing

and Physical Layer Interface (Non-Memory Controller Design). Added Figure 1-57

through Figure 1-59 in Write Path. In Table 1-91, removed DISABLED option from

RTT_NOM for DDR3_SDRAM, changed RTT_NOM to RTT_WR in RTT_WR,

updated SIM_BYPASS_INIT_CAL, and updated table note 2. In Table 1-92, updated

tZQI and added USER_REFRESH. Added Table 1-93. In Configuration, updated

constraints example and removed paragraph about SCL and SDA.

• Chapter 2: Added step 2 to MIG Output Options, page 181. Added Input Clock

Period description in Controller Options, page 184. Added Debug Signals Control

and Internal V

ref Selection options to FPGA Options, page 187. Added I/O Planning

Options, page 189. In System Pins Selection, page 192, changed cal_done signal to

init_calib_complete and error signal to tg_compare_error. Replaced Table 2-2.

Changed file names in Table 2-8. Updated signal names in Figure 2-23, Figure 2-24,

and Figure 2-25. Updated signal names in Table 2-10. Added CPT_CLK_CQ_ONLY

and updated value for SIM_BYPASS_INIT_CAL in Table 2-13. Added Table 2-14.

Updated pinout rules in Pinout Requirements, page 221. Added paragraph about

DCI and IN_TERM after Table 2-15. Added Debugging QDRII+ SRAM Designs,

page 224.

• Chapter 3: Added step 2 to MIG Output Options, page 248. Added Input Clock

Period description in Controller Options. Added Debug Signals Control and Internal

Vref Selection options to FPGA Options, page 253. In System Pins Selection, changed

cal_done signal to init_calib_complete and error signal to tg_compare_error. Changed

file names in Table 3-8. Removed Table 3-12, which contained Reserved signals not

used. Added rst_phaser_ref to Table 3-12. Removed PHY-Only Interface section. In

Table 3-15, added RLD_ADDR_WIDTH, MEM_TYPE, CLKIN_PERIOD, and

SIMULATION, and renamed CLKFBOUT_MULT, CLKOUT0_DIVIDE,

CLKOUT1_DIVIDE, CLKOUT2_DIVIDE, and CLKOUT3_DIVIDE. Updated

Table 3-16. Added paragraph about DCI and IN_TERM after Table 3-27.

•Added Chapter 4, Multicontroller Design.

Date Version Revision

7 Series FPGAs Memory Interface Solutions www.xilinx.com UG586 October 16, 2012

01/18/12 1.3 MIG 1.4 release. Updated ISE Design Suite version to 13.4. Updated GUI screen captures

throughout document.

• Chapter 1: Added support for DDR2 SDRAM. Added option 3 to MIG Output

Options. Added EDK Clocking. Updated Simulation Considerations. Added

Replaced Figure 1-26 and Figure 1-50.

• Chapter 2: Removed Input Clock Period option from Controller Options. Added

Memory Options. Added Reference Clock option to FPGA Options. Updated Debug

Signals.

• Chapter 3: Removed Input Clock Period option from Controller Options. Added

Input Clock Period option to Memory Options. Added Reference Clock option to

FPGA Options. Added Debugging RLDRAM II and RLDRAM III Designs.

04/24/12 1.4 MIG 1.5 release. Updated ISE Design Suite version to 14.1. Updated GUI screen captures

throughout document. Replaced IODELAYCTRL with IDELAYCTRL throughout.

• Chapter 1: Added I/O Power Reduction option to FPGA Options. Revised I/O

standards for sys_rst option in Bank Selection. Added Creating ISE Project Navigator

Flow for MIG Example Design, Power-Saving Features, Multi-Purpose Register Read

Leveling, OCLKDELAYED Calibration, Upsizing and Downsizing, and External Vref

sections. Changed bits [16:15] to from Rank Count to Reserved in the PHY Control

word. Revised maximum setting of NUM_DQ_PINS in Table 1-11. Revised

Figure 1-37 flowchart. Removed RankSel[1:0] from Figure 1-38 and Figure 1-40.

Added mc_odt and mc_cke to Table 1-86. Replaced AXI Addressing. Updated

REFCLK_FREQ, RANK_WIDTH, and WRLVL in Table 1-91. Added

DATA_IO_PRIM_TYPE to Table 1-92. Added bullet about DQSCC pins to Bank and

Pin Selection Guides for DDR3 Designs. Changed DIFF_SSTL_15 to DIFF_SSTL18_II

and SSTL15 to SSTL18_II.

• Chapter 2: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. Revised

I/O standards for sys_rst option in System Pins Selection. Revised the

PHY_BITLANE parameters in Table 2-14.

Added System Clock, PLL Location, and

Constraints and Configuration sections.

• Chapter 3: Changed DIFF_SSTL_15 to DIFF_HSTL_I and SSTL15 to HSTL_I. to

Revised I/O standards for sys_rst option in System Pins Selection. Added the Write

Calibration, System Clock, PLL Location, and Constraints, and Configuration

sections. Revised the PHY_BITLANE parameters in Table 3-16. In Table 3-31, added

dbg_wrcal_sel_stg[1:0], dbg_wrcal[63:0], dbg_wrcal_done[2:0],

dbg_wrcal_po_first_edge[5:0], dbg_wrcal_po_second_edge[5:0], and

dbg_wrcal_po_final[5:0].

06/13/12 1.5 Revised the recommended total electrical delay on CK/CK# relative to DQS/DQS# on

page 150.

07/25/12 1.6 MIG 1.6 release. Updated ISE Design Suite version to 14.2. Updated GUI screen captures

throughout document.

• Chapter 1: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA

Options, page 24. Changed the parameters nCK_PER_CLK, tZQI, SYSCLK_TYPE,

REFCLK_TYPE, and APP_DATA_WIDTH. Added bulleted item about multiple CK

outputs to Bank and Pin Selection Guides for DDR3 Designs, page 144. Updated Trace

Lengths, page 150 and Termination, page 155.

• Chapter 2: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA

Options, page 187. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.

• Chapter 3: Added No Buffer, Use System Clock, and Sample Data Depth in FPGA

Options, page 187. Changed the parameters SYSCLK_TYPE and REFCLK_TYPE.

• Chapter 5: Added new chapter on migrating to Vivado Design Suite.

Date Version Revision

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