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NAND FLASH MEMORY
TECHNOLOGIES

IEEE Press
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Piscataway, NJ 08854
IEEE Press Editorial Board
Tariq Samad, Editor in Chief
George W. Arnold Vladimir Lumelsky Linda Shafer
Dmitry Goldgof Pui-In Mak Zidong Wang
Ekram Hossain Jeffrey Nanzer MengChu Zhou
Mary Lanzerotti Ray Perez George Zobrist
Kenneth Moore, Director of IEEE Book and Information Services (BIS)
Technical Reviewers
Joe E Brewer, PE, Electronic Engineering Consultant
Chandra Mouli, Director, R&D Device Technology, Micron Technology Inc, Boise ID, USA
Gabriel Molas, CEA LETI Minatec, Grenoble, France

NAND FLASH MEMORY
TECHNOLOGIES
SEIICHI ARITOME
IEEE Press Series on Microelectronic Systems

Copyright © 2016 by The Institute of Electrical and Electronics Engineers, Inc.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved
Published simultaneously in Canada
No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
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Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in
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Library of Congress Cataloging-in-Publication Data is available.
ISBN: 978-1-119-13260-8
Printed in the United States of America
10987654321

CONTENTS
Foreword xi
Preface xv
Acknowledgments xvii
About the Author xix
1 Introduction 1
1.1 Background, 1
1.2 Overview, 8
References, 10
2 Principle of NAND Flash Memory 17
2.1 NAND Flash Device and Architecture, 17
2.1.1 NAND Flash Memory Cell Architecture, 17
2.1.2 Peripheral Device, 19
2.2 Cell Operation, 21
2.2.1 Read Operation, 21
2.2.2 Program and Erase Operation, 21
2.2.3 Program and Erase Dynamics, 28
2.2.4 Program Boosting Operation, 31
2.3 Multilevel Cell (MLC), 34
2.3.1 Cell V
t
Setting, 34
References, 35
v
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