南亚 DDR3 4Gb 内存芯片技术规格解析

DDR3

datasheet

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"Nanya南亚DDR3规格书详细介绍了其4Gb DDR3(L)动态随机存取存储器，这是一种高速CMOS SDRAM，包含4,294,967,296位数据。它内部配置为八银行结构。4Gb芯片有两种组织形式：64Mbit x 8 I/O x 8 banks 和 32Mbit x16 I/O x 8 banks。这些同步设备实现了高达2133 Mb/sec/pin的双倍数据速率传输速度，适用于通用应用。芯片设计符合所有关键DDR3(L) DRAM特性，控制和地址输入与外部提供的差分时钟同步，输入在时钟交叉点（CK上升沿和CKneg下降沿）被捕捉。所有I/O与单端DQS或差分DQS对源同步。设备运行时只需1.5V ± 0.075V或1.35V -0.067V/+0.1V的电源，并提供BGA封装。文档还提到了DDR3(L)的特性，如8n预取架构、差分时钟和数据 strobe、双数据速率操作、数据完整性保护、自动自刷新、部分阵列自刷新以及节能模式等。" DDR3内存是一种先进的存储技术，DDR3L是低功耗版本，兼容于DDR3。此规格书中详细描述了4Gb DDR3L芯片的规格和功能，包括以下要点： 1. **内存容量与组织**：4Gb DDR3 DRAM提供64Mbit x 8 I/O x 8 banks和32Mbit x16 I/O x 8 banks两种组织形式，这意味着它可以提供不同的存储密度和接口宽度。 2. **传输速度**：该芯片设计为实现最高2133 Mb/sec/pin的数据传输速率，这是通过双倍数据速率技术在每个时钟周期的上升沿和下降沿传输数据来实现的。 3. **同步与时钟**：所有的输入信号都是与一对外部差分时钟同步的，且在时钟交叉点被采样，确保了高速传输下的精确性。 4. **电源管理**：DDR3L支持1.5V和1.35V两种电源电压，其中1.35V版本是低功耗设计，同时与1.5V DDR3兼容，但1.35V DDR3L-RS例外。 5. **数据完整性**：包括自动自刷新（ASR）和自动刷新模式，通过内置温度传感器保证数据的完整性。此外，当温度超过85°C时，需要外部以2倍刷新率进行刷新。 6. **节能模式**：支持部分数组自刷新（PASR），允许只刷新正在使用的内存部分，从而节省电力。 7. **其他特性**：支持8n预取架构，即每次时钟周期读取或写入8位数据；DQS和DQS差分数据 strobe 用于数据的精确时序控制；DM数据掩码信号用于提高数据传输的可靠性。这份规格书对于理解DDR3 DRAM的工作原理、性能参数以及如何在系统中正确使用这些内存是非常重要的参考资料。无论是设计电路板、编程还是故障排查，都离不开这些详细的技术指标和功能描述。

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DDR3(L) 4Gb SDRAM

NT5CB(C)512M8DN / NT5CB(C)256M16DP

Version 2.2 16 Nanya Technology Cooperation ©

MOD

Timing

CKE

MRS NOP NOP NOP NOPCMD

ADDR

tMOD

Non

MRS

VAL

Old Setting

Updating Setting

New Setting

VAL

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8DN / NT5CB(C)256M16DP

Version 2.2 18 Nanya Technology Cooperation ©

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

command via A12/.

Burst Type and Burst Order

Burst

Length

Read

Write

Starting

Column

Address

(A2,A1,A0)

Burst type:

Sequential

(decimal)

A3 = 0

Burst type:

Interleaved

(decimal)

A3 = 1

Note

Chop

Read

0,0,0

0,1,2,3,T,T,T,T

1,2,3

0,0,1

1,2,3,0,T,T,T,T

1,0,3,2,T,T,T,T

0,1,0

2,3,0,1,T,T,T,T

0,1,1

3,0,1,2,T,T,T,T

3,2,1,0,T,T,T,T

1,0,0

4,5,6,7,T,T,T,T

1,0,1

5,6,7,4,T,T,T,T

5,4,7,6,T,T,T,T

1,1,0

6,7,4,5,T,T,T,T

1,1,1

7,4,5,6,T,T,T,T

7,6,5,4,T,T,T,T

Write

0,V,V

0,1,2,3,X,X,X,X

1,2,4,5

1,V,V

4,5,6,7,X,X,X,X

Read

0,0,0

0,1,2,3,4,5,6,7

0,0,1

1,2,3,0,5,6,7,4

1,0,3,2,5,4,7,6

0,1,0

2,3,0,1,6,7,4,5

0,1,1

3,0,1,2,7,4,5,6

3,2,1,0,7,6,5,4

1,0,0

4,5,6,7,0,1,2,3

1,0,1

5,6,7,4,1,2,3,0

5,4,7,6,1,0,3,2

1,1,0

6,7,4,5,2,3,0,1

1,1,1

7,4,5,6,3,0,1,2

7,6,5,4,3,2,1,0

Write

V,V,V

0,1,2,3,4,5,6,7

2,4

Note:

1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8

mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected

on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that

during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.

3. T: Output driver for data and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

5. X: Do not Care.

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8DN / NT5CB(C)256M16DP

CAS Latency

The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in

clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does

not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency

(CL); RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM

manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.

Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK

must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous

operations.)

Write Recovery

The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)

and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be

equal or larger than tWR (min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

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